Senior ASIC Design Verification Engineer
14 hours ago
We are seeking a highly skilled Senior ASIC Design Verification Engineer to join our team at L&T Technology Services. As a key member of our design verification team, you will be responsible for defining and implementing IP/SoC verification plans, building verification test benches, and driving design verification to closure.
Responsibilities- Verification Planning: Develop and implement IP/SoC verification plans to ensure comprehensive verification of ASIC designs.
- Test Bench Development: Design and build verification test benches to enable IP/sub-system/SoC level verification.
- Functional Testing: Develop functional tests based on verification test plans to ensure first-pass success in ASIC development cycles.
- Design Verification: Drive design verification to closure based on defined verification metrics, partnering with the design team to resolve functional failures.
- Continuous Improvement: Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies.
- Education: Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
- Experience: 5+ years of hands-on experience in System Verilog/UVM methodology and/or C/C++ based verification.
- Track Record: Proven track record of 'first-pass success' in ASIC development cycles.
- Skills: Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Infrastructure: Experience in architecting and implementing design verification infrastructure and executing the full verification cycle.
- UVM Experience: Experience in developing UVM based verification environments from scratch.
- GPU/CPU Verification: Experience verifying GPU/CPU designs.
- Micro-Architectural Verification: Experience with micro-architectural performance verification.
- Data-Center Applications: Experience with design verification of data-center applications like video, AI/ML, and networking designs.
- ARM/RISC-V Verification: Experience verifying ARM/RISC-V based sub-systems or SoCs.
- High-Speed Interfaces: Experience with verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.
- Formal Verification: Experience with one or more of the following areas along with functional verification - SV assertions, formal, emulation.
- Revision Control Systems: Experience working with revision control systems like Mercurial (Hg), Git, or SVN.
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