CPU/AI Physical Design Block Lead

4 weeks ago

Santa Clara, United States Tenstorrent Full time

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Physical design for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.

This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.

Responsibilities:

  • Own physical design partitions and drive the design to closure
  • Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
  • Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
  • Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
  • Collaborate with RTL designers to explore design options, conduct PD experiments, analyze results, understand tradeoffs and arrive at optimal design solutions
Experience & Qualifications:
  • BS/MS/PhD in EE/ECE/CE/CS
  • Expertise in optimizing PPA for high performance and low power designs
  • Excellent understanding of logic design fundamentals and gate/transistor level implementation
  • Prior experience with optimizing RTL for timing/power
  • Hands-on experience with synthesis, block and chip level implementation, timing closure and ECO flows
  • Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
  • Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
  • Strong programming skills in Tcl/Perl/Shell/Python
  • Knowledge of CPU or AI/ML Accelerator Micro Architecture is a plus
  • Exposure to DFT is an asset


Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.

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