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Senior Physical Design Engineer

4 months ago

Santa Clara, United States Tenstorrent Full time

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

This role is hybrid, based out of Santa Clara, CA, Austin, TX or Ft. Collins, CO.

Physical design for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.

Responsibilities:

  • Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
  • Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
  • Discussions with 3rd party IP providers, foundry partners and design services
  • End to end tasks from flow development to sign-off
  • Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results

Experience & Qualifications

  • BS/MS/PhD in EE/ECE/CE/CS
  • Hands-on experience with synthesis, block and chip level implementation with industry standard PnR flows and tools
  • Strong experience in SOC/ASIC/GPU/CPU design flows on taped out designs, expertise in timing closure at block/chip levels and ECO flows
  • Experience with back-end design tools such as Primetime, Innovus, RedHawk, etc.
  • Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
  • Strong programming skills in Tcl/Perl/Shell/Python
  • Excellent understanding of logic design fundamentals and gate/transistor level implementation
  • Exposure to DFT is an asset
  • Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
  • Strong problem solving and debug skills across various levels of design hierarchies
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.   Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.   Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.   As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.