Current jobs related to ASIC/RTL Design Engineer - Santa Clara - CV Library

  • ASIC Design Engineer

    2 months ago

    Santa Clara, United States Palo Alto Networks Full time

    This role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Design Engineer - RTL Quality Checks - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate...

  • ASIC Design Engineer Specialist

    4 weeks ago

    Santa Clara, California, United States Palo Alto Networks Full time

    Job OverviewWe are seeking a highly skilled ASIC Design Engineer - RTL Quality Checks to join our team at Palo Alto Networks. This role is a great opportunity for a talented individual who has the desire to work in a fast-growing company with a truly international environment.Key ResponsibilitiesAs an ASIC Design Engineer - RTL Quality Checks, you will be...

  • ASIC Design Engineers

    2 weeks ago

    Santa Clara, United States P Chappel Associates Inc Full time

    Front-End ASIC Design Engineer - Milpitas, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design department....

  • Highly Skilled ASIC Design Engineer for Innovative Projects

    4 weeks ago

    Santa Clara, California, United States Infobahn SoftWorld Inc Full time

    We are seeking an experienced ASIC/RTL Design Engineer to join our team at Infobahn SoftWorld Inc. in San Jose, CA.Estimated Annual Salary: $175,000 - $225,000Job DescriptionThis is a 12+ months contract position that involves designing and implementing digital logic functions for efficient test and debug. The ideal candidate will have a proven track record...

  • ASIC Design Verification Engineer

    1 month ago

    Santa Clara, United States MRL Consulting Full time

    ASIC Design Verification Engineer Location: San Jose, California Role Overview: We are seeking a skilled ASIC Design Verification Engineer to provide design verification services for our System on Chip (SoC) projects. Key Responsibilities: Develop test benches using System Verilog UVM. Create test plans and test cases, including functional coverage,...

  • RTL Quality Assurance Expert

    4 weeks ago

    Santa Clara, California, United States Palo Alto Networks Full time

    About the RoleAs an ASIC Design Engineer - RTL Quality Checks, you will play a pivotal role in the success of our organization. This role requires a high level of expertise in RTL quality checks and a strong understanding of complex digital circuits. You will be working in a collaborative environment, contributing to the daily operations of the ASIC...

  • ASIC Physical Design Engineer

    2 months ago

    Santa Clara, United States Palo Alto Networks Full time

    This role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Physical Design Engineer - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate with a...

  • ASIC Implementation Engineer

    4 months ago

    Santa Clara, United States L&T Technology Services Full time

    Responsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...

  • Complex Digital Circuit Designer

    4 weeks ago

    Santa Clara, California, United States Palo Alto Networks Full time

    Job DescriptionWe are seeking a highly skilled ASIC Design Engineer - RTL Quality Checks to join our team at Palo Alto Networks. As an ASIC Design Engineer - RTL Quality Checks, you will be responsible for performing RTL sign-off checks on complex blocks with multiple clocks and resets. This role requires a high level of expertise in RTL quality checks and a...

  • RTL Design Engineer

    4 weeks ago

    Santa Clara, CA, United States Yoh Services LLC Full time

    RTL Design Engineer Looking for a solid RTL Design Engineer who has a strong background in supporting RISC-V houses. The primary technology will be focused around SOCs that are built around ML Accelerators. This person should have a solid background in RTL Design and also have an understanding of verification flows. This person should be a strong engineer...

  • ASIC Design Engineer

    4 weeks ago

    Santa Clara, United States Apple Full time

    ASIC Design Engineer - Memory Cache ControllerSanta Clara, California, United StatesHardwareApple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth, and capacity, we are presented with...

  • Expert ASIC Design Engineer

    4 weeks ago

    Santa Clara, California, United States Ambarella Inc. Full time

    At Ambarella Inc., we are seeking a highly skilled Sr. ASIC Design Engineer to join our team.About the RoleWe are looking for a seasoned professional with expertise in designing and implementing video compression logic, image processing logic, vector processing, and neural network accelerator logics, processor cores, and memory sub-systems in Verilog and...

  • Senior ASIC Design Engineer Lead

    4 weeks ago

    Santa Clara, California, United States Qualcomm Full time

    Job OverviewWe are seeking a highly skilled and experienced Senior ASIC Design Engineer Lead to join our team at Qualcomm. This role will be responsible for leading the design and development of advanced ASICs, collaborating with cross-functional teams, and ensuring the successful execution of projects.

  • ASIC Design Engineer

    2 months ago

    Santa Clara, United States Apple Inc. Full time

    ASIC Design Engineer - Memory Cache Controller Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with...

  • Senior ASIC Design Verification Engineer

    1 week ago

    Santa Clara, California, United States Qualcomm Full time

    Job DescriptionWe are seeking a highly skilled and experienced Senior ASIC Design Verification Engineer to lead our design verification team in the development of cutting-edge wireless connectivity products. As a key member of our Engineering Group, you will be responsible for overseeing the entire design verification process, from concept to delivery.About...

  • ASIC Design Engineer

    1 month ago

    Santa Clara, United States Apple Inc. Full time

    ASIC Design Engineer - Memory Cache ControllerTo view your favorites, sign in with your Apple Account.Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are...

  • RTL Designer and Verifier

    1 week ago

    Santa Clara, California, United States Veear Full time

    Join Our TeamWe are seeking a highly skilled RTL Designer and Verifier to join our team at Veear. As a key member of our engineering team, you will be responsible for designing and verifying complex digital logic circuits.Key Responsibilities:Collaborate with architects and designers to ensure design verification meets high standards.Design and implement...

  • Advanced ASIC Design Specialist

    1 week ago

    Santa Clara, California, United States Qualcomm Full time

    Job Overview:We are seeking an experienced Advanced ASIC Designer to join our team at Qualcomm. As a key member of the Integrated Wireless Technology group, you will work on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates, and power reduction techniques.Responsibilities:Leverage advanced ASIC...

  • Senior ASIC Design Engineer for High-Performance CPU Development

    4 weeks ago

    Santa Clara, California, United States CyberCoders Full time

    CyberCoders Seeks Senior ASIC Design EngineerWe are a leading supplier of embedded processor intellectual property, and we're looking for an experienced Senior ASIC Design Engineer to join our VLSI team. The ideal candidate will have a passion for technical advances in CPU architecture and a keen interest in tackling present-day verification...

  • Micro-Architecture Specialist

    1 week ago

    Santa Clara, California, United States P Chappel Associates Inc Full time

    Responsibilities and QualificationsThis is a challenging role that requires a highly skilled and experienced Front-End ASIC Design Engineer. Key responsibilities include:Supporting customer designs through all phases of ASIC executionEnsuring designs meet product performance requirements by performing related tasksContributing to microarchitecture, RTL...

ASIC/RTL Design Engineer

1 month ago

Santa Clara, United States CV Library Full time

Location: San Jose, CA

100% onsite (4 days a week in office, Friday optional)

Spotlight call notes:

  1. RTL coding experience
  2. Front end RTL design
  3. One of the positions requires good knowledge of Python
  4. There may be some flexibility on the max bill rate

Top 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have.

KEY RESPONSIBILITIES:
  1. Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
  2. Collaborate with architecture and hardware teams to understand the requirements.
  3. Work with verification and physical design teams to achieve high quality design and successful tape out.
  4. Design and implement logic functions that enable efficient test and debug.
  5. Participate in silicon bring-up for features owned.
  6. Contribute in cross-functional teams to solve Client problems across multiple functional areas in development of required features.
  7. Implement automation to increase design team efficiency.
EXPERIENCE:
  1. 5-6+ years' experience
  2. Must have proven track record of ASIC design on several production tape-outs.
  3. Experience in Designing RTL block for an SOC.
  4. Experience in integrating ASIC IP into an SOC.
  5. Experience with Arm architecture and APB, AXI, CHI protocols.
  6. Experience with synthesis, static timing analysis & optimizations.
  7. Experience with design involving Interconnects.
  8. Experience writing timing constraints and exceptions.
  9. Experience with automation using scripting techniques such as PERL, Python or Tcl.
  10. Ability to develop clear and concise engineering documentation.
  11. Experience in Power-saving techniques.
  12. Ability to organize and present complex technical information.
  13. Strong verbal and written communication skills.
#J-18808-Ljbffr