ASIC Design Engineer
3 weeks ago
Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth.In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy
Description
Participate in Cache micro architecture development from specifications found from architecture guideline and model analysis.Explore architecture trade-offs in system performance, area, and power consumption along with the performance analysis team.Develop/debug RTL design of different sections of the cache.Work with physical design team to close timing of the same.
Key Qualifications
- Development of memory systems.
- Experience in PPA (performance/power/area) analysis.
- Knowledge of dedication coherent memory system or interconnect architectures.
- Strong cache design background including good understanding of different memory organizations and tradeoffs.
- Knowledge of dedication memory subsystem and dram controller.
- Hands on Experience with multi-processor cache coherence protocols
Bachelors Degree + 10 Years of Experience.
- At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $175,800 and $312,200, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
#J-18808-Ljbffr-
Senior ASIC Digital Design Engineer
1 month ago
Santa Clara, California, United States Qualcomm Full timeJob SummaryQualcomm is seeking a highly skilled Senior ASIC Digital Design Engineer to join our team. As a key member of our Engineering Group, you will be responsible for defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP (block/SoC) development for high-performance, high-quality, low-power products.Key...
-
Senior ASIC Floorplan Design Engineer
3 weeks ago
Santa Clara, United States NVIDIA Corporation Full timeSenior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing...
-
ASIC Physical Design Engineer
3 weeks ago
Santa Clara, United States Palo Alto Networks Full timeThis role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Physical Design Engineer - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate with a...
-
ASIC Design Engineer, System-ASIC
3 weeks ago
Santa Clara, United States NVIDIA Full timeNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...
-
Senior ASIC Design Engineer
3 weeks ago
Santa Clara, United States NVIDIA Full timeWe are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial...
-
Senior ASIC Design Engineer
6 months ago
Santa Clara, United States NVIDIA Full timeWe are now looking for a Senior ASIC Design Engineer.NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial...
-
Senior ASIC Design Engineer
1 month ago
Santa Clara, California, United States Astera Labs Full timeAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure.Our Intelligent Connectivity Platform integrates PCIe, CXL, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is...
-
ASIC Design Verification Engineer
5 hours ago
Santa Clara, United States MRL Consulting Full timeASIC Design Verification Engineer Location: San Jose, California Role Overview: We are seeking a skilled ASIC Design Verification Engineer to provide design verification services for our System on Chip (SoC) projects. Key Responsibilities: Develop test benches using System Verilog UVM. Create test plans and test cases, including functional coverage,...
-
ASIC/RTL Design Engineer
6 days ago
Santa Clara, United States CV Library Full timeLocation: San Jose, CA100% onsite (4 days a week in office, Friday optional)Spotlight call notes:RTL coding experienceFront end RTL designOne of the positions requires good knowledge of PythonThere may be some flexibility on the max bill rateTop 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to...
-
ASIC Design Engineer
3 weeks ago
Santa Clara, United States Palo Alto Networks Full timeThis role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Design Engineer - RTL Quality Checks - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate...
-
Senior Design Engineer
7 days ago
Santa Clara, United States NVIDIA Corporation Full timeSenior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC‘s and GPU‘s. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC,...
-
Senior Design Engineer
3 days ago
Santa Clara, United States NVIDIA Corporation Full timeSenior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC‘s and GPU‘s. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC,...
-
Senior ASIC Design Engineer
4 weeks ago
Santa Clara, California, United States Apple Full timeDescriptionAs a key member of the System-on-Chip (SoC) Design team at Apple, you will play a critical role in the development of next-generation SOC architectures. You will be responsible for designing and implementing high-speed digital ASICs, with a focus on fabric interconnects.Key Responsibilities:Analyze architectural requirements of next-generation...
-
High Performance ASIC Design Expert
2 weeks ago
Santa Clara, California, United States NVIDIA Full timeWe are seeking a talented ASIC Design Efficiency Engineer to join our team at NVIDIA. This position offers the opportunity to design hardware accelerators and processors for our next-generation mobile, embedded, and datacenter platforms.About the Role:Develop innovative HW, GPU, and system designs to extend state-of-the-art performance and...
-
ASIC Implementation Engineer
2 months ago
santa clara, United States L&T Technology Services Full timeResponsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...
-
ASIC Implementation Engineer
3 months ago
Santa Clara, United States L&T Technology Services Full timeResponsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...
-
ASIC Implementation Engineer
1 month ago
santa clara, United States L&T Technology Services Full timeResponsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...
-
Senior ASIC Verification Engineer
2 days ago
Santa Clara, United States NVIDIA Full timeWe are looking for a Senior Verification Engineer to join our Display Team! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of...
-
Principal Design Verification Engineer
3 weeks ago
Santa Clara, United States Astera Labs Full timeAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture...
-
Design Verification Engineer
1 week ago
Santa Clara, United States HCLTech Full timeJob Title: Verification Engineer (AXI)Location: Santa Clara, CA OR Austin, TXSalary Range: $80-90/hr on W2Job Type: Full-timeCompany Overview:HCL Technologies is a next-generation global technology company that helps enterprises reimagine their businesses for the digital age. Our technology products and services are built on four decades of innovation, with...