ASIC Design Engineer

Job OverviewWe are seeking a highly skilled ASIC Design Engineer - RTL Quality Checks to join our team at Palo Alto Networks. This role is a great opportunity for a talented individual who has the desire to work in a fast-growing company with a truly international environment.Key ResponsibilitiesAs an ASIC Design Engineer - RTL Quality Checks, you will be...

Senior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC, allowing...

This role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Physical Design Engineer - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate with a...

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...

Job OverviewWe are seeking a highly skilled and experienced Senior ASIC Design Engineer Lead to join our team at Qualcomm. This role will be responsible for leading the design and development of advanced ASICs, collaborating with cross-functional teams, and ensuring the successful execution of projects.

We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial...

We are now looking for a Senior ASIC Design Engineer.NVIDIA is seeking ASIC Design Engineers to implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a multifaceted, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial...

ASIC Design Verification Engineer Location: San Jose, California Role Overview: We are seeking a skilled ASIC Design Verification Engineer to provide design verification services for our System on Chip (SoC) projects. Key Responsibilities: Develop test benches using System Verilog UVM. Create test plans and test cases, including functional coverage,...

Location: San Jose, CA100% onsite (4 days a week in office, Friday optional)Spotlight call notes:RTL coding experienceFront end RTL designOne of the positions requires good knowledge of PythonThere may be some flexibility on the max bill rateTop 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to...

This role is a contract assignment at Palo Alto Networks. Contractors will not be employed by Palo Alto Networks but through our trusted staffing partners. Palo Alto Networks is looking for a ASIC Design Engineer - RTL Quality Checks - Contractor to work with the ASIC team and is a great opportunity for a talented individual who has the desire to associate...

CyberCoders Seeks Senior ASIC Design EngineerWe are a leading supplier of embedded processor intellectual property, and we're looking for an experienced Senior ASIC Design Engineer to join our VLSI team. The ideal candidate will have a passion for technical advances in CPU architecture and a keen interest in tackling present-day verification...

We are seeking an experienced ASIC/RTL Design Engineer to join our team at Infobahn SoftWorld Inc. in San Jose, CA.Estimated Annual Salary: $175,000 - $225,000Job DescriptionThis is a 12+ months contract position that involves designing and implementing digital logic functions for efficient test and debug. The ideal candidate will have a proven track record...

Senior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC‘s and GPU‘s. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC,...

Senior ASIC Floorplan Design EngineerWe are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC‘s and GPU‘s. This position offers you a unique opportunity to craft and to influence the design and development of the next generation GPU and SoC,...

At Ambarella Inc., we are seeking a highly skilled Sr. ASIC Design Engineer to join our team.About the RoleWe are looking for a seasoned professional with expertise in designing and implementing video compression logic, image processing logic, vector processing, and neural network accelerator logics, processor cores, and memory sub-systems in Verilog and...

We are seeking a talented ASIC Design Efficiency Engineer to join our team at NVIDIA. This position offers the opportunity to design hardware accelerators and processors for our next-generation mobile, embedded, and datacenter platforms.About the Role:Develop innovative HW, GPU, and system designs to extend state-of-the-art performance and...

Experis is seeking a Senior ASIC Verification Expert to join their team in Santa Clara, CA. This is an onsite/hybrid role that requires collaboration with architects, hardware engineers, and firmware engineers to understand new features to be verified.Key Responsibilities:Develop test plan documentation for interactions with other features, hardware,...

Responsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...

Responsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...

Responsibilities:Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them.Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic...