ASIC Design Verification Engineer
17 hours ago
Location: San Jose, California
Role Overview:
We are seeking a skilled ASIC Design Verification Engineer to provide design verification services for our System on Chip (SoC) projects.
Key Responsibilities:
- Develop test benches using System Verilog UVM.
- Create test plans and test cases, including functional coverage, assertions, coverage properties, coverage groups, and coverage collections.
- Set up and debug regressions at both the RTL and gate simulation levels in collaboration with the design team.
- Over 10 years of experience in Design Verification.
- Extensive knowledge of System Verilog, UVM, and verification coverage matrices.
- Familiarity with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP tools.
- Strong expertise in PCIe/CXL protocols, including PHY, DLLP, and TLP layers.
- In-depth understanding of peripheral protocols such as UART, I2C, and SPI Flash.
- Proficiency in Perl scripting.
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