ASIC Physical Design, Sr Staff Engineer

Found in: Jooble US O C2 - 2 weeks ago


Sunnyvale CA, United States Synopsys, Inc. Full time

As a ASIC Physical Implementation, Sr Staff Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies with a specific focus on very advanced high speed SERDES platforms.

In this role, you will be responsible for the Physical Implementation of high speed interface IPs and test-chips, driving all aspects from RTL to GDS including timing and physical sign-off. You will work in close interaction and collaborative team work with multiple functional groups (front end digital, analog design and layout, CAD) and the product team.

The successful candidate will have the following: 10 + years of digital or physical design experience with recent contribution to project tape-outs, as a technical driver and/or project head.
  • Intimate understanding of the full design cycle from RTL to GDSII, including chip level.
  • Experience with advanced FinFET nodes, TSMC 16 nanometer or below, including low-power design techniques
  • A solid engineering understanding of the underlying concepts of digital design and architecture, implementation flows and physical and timing signoff
  • Development of timing constraints and design architectures to ensure on-time delivery, and to meet or exceed power and area targets
  • Excellent communication skills, ability to think and communicate at different levels of abstraction, with peer groups as well as customers.
  • Methodology guided with excellent software and scripting skills (Perl, Tcl, Python); understanding of CAD automation methods.
  • Solid understanding of the challenges inherent in analog/digital interfaces.
  • Autonomous, and able to cope with interrupts.

Requirements:
  • MSEE and 8+ years or BSEE and 10+ years
  • Previous project leadership experience
  • Solid understanding of digital / mixed signal verification flows and SOC integration challenges.
  • Ability to travel internationally as required.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Stay Connected: Join our Talent Community
#J-18808-Ljbffr

  • Sunnyvale, United States SpaceX Full time

    SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...

  • ASIC Physical Design Engineer, Proto

    Found in: Jooble US O C2 - 3 days ago


    San Jose, CA, United States Block Full time

    Job Description Apply promptly! A high volume of applicants is expected for the role as detailed below, do not wait to send your CV. Team Overview We believe everyone should be able to participate and thrive in the economy. We believe bitcoin plays an essential role in the future of payments and the world’s economy. We believe that the status quo of...

  • Sr. ASIC Design Engineer

    Found in: Jooble US O C2 - 2 weeks ago


    San Jose, CA, United States ScaleFlux Full time

    We are looking for Sr. ASIC Design Engineer to join our rapidly growing ASIC design team focused on high performance data center infrastructure ASIC design and SOC development. The ideal candidate for this role shares our passion for creating innovative technologies, and thrives in a highly dynamic, fast-paced, results-driven environment. We are looking for...

  • ASIC Physical Design, Principal Engineer

    Found in: Jooble US O C2 - 3 days ago


    Sunnyvale, CA, United States Synopsys, Inc. Full time

    As a ASIC Physical Implementation, Principal Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies...

  • Staff/Sr. Staff PHY Design Engineer

    Found in: Jooble US O C2 - 2 weeks ago


    San Jose, CA, United States InnoPhase IoT Full time

    Staff/Sr. Staff PHY Design Engineer Job Description: Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design. You will be involved in the design development cycle, which includes participating in high-level product specifications, RTL development, working closely with Algorithm and...

  • RTL ASIC Design Engineer

    Found in: Jooble US O C2 - 2 days ago


    Sunnyvale, CA, United States Wipro Full time

    RTL ASIC Design Engineers with 8 to 15+ years of experience. No of Openings: 2 Sunnyvale, CA Job Description: 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must. Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB...

  • ASIC Staff Design Engineer

    Found in: Jooble US O C2 - 3 days ago


    Menlo Park, CA, United States Cerncourier Full time

    SLAC National Accelerator Laboratory seeks an Application Specific Integrated Circuit (ASIC) design engineer within the Integrated Circuits Department of the Instrumentation Division of the Technology Innovation Directorate. The IC department develops state-of-the-art, low-noise and low-power front-end Application Specific Integrated Circuits (ASICs) to...

  • RTL ASIC Design Engineer

    Found in: Appcast US C2 - 1 week ago


    Sunnyvale, United States Wipro Full time

    RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

  • RTL ASIC Design Engineer

    Found in: Appcast Linkedin GBL C2 - 2 weeks ago


    Sunnyvale, United States Wipro Full time

    RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

  • ASIC Design Engineer

    Found in: Jooble US O C2 - 3 days ago


    Santa Clara, CA, United States P. Chappel Associates, Inc. Full time

    Front-End ASIC Lead Design Engineer - Santa Clara, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

  • Principal Engineer/Manager, ASIC Physical Design

    Found in: Jooble US O C2 - 1 week ago


    San Diego, CA, United States InnoPhase Full time

    About InnoPhase, Inc. INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless...


  • San Jose, CA, United States Recogni Full time

    Artificial intelligence (AI) is transforming our world. Recogni is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We...

  • Principal Engineer/Manager, ASIC Physical Design

    Found in: Jooble US O C2 - 1 week ago


    San Jose, CA, United States InnoPhase Full time

    As a Principal Engineer/Manager, ASIC Physical Design , you will be responsible for providing technical leadership in developing novel/game-changing cellular infrastructure radio and ASIC solutions. You will be a key contributor to our solutions features, architectures, device functional specifications, and performance. Your primary responsibilities...


  • Sunnyvale, United States META Full time

    The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. ASIC Engineering Manager, Design Verification Responsibilities Manage an ASIC design...

  • ASIC Design Engineer, Hardware Compute Group

    Found in: Talent US C2 - 2 weeks ago


    Sunnyvale, United States Amazon.com Services LLC Full time

    As a ASIC Design Engineer, you work with a team creating hardware accelerator IP to be deployed in a range of Amazon devices. You will develop hardware IP to accelerate applications in machine learning, computer vision and robotics. You will work closely with scientists, SoC Architects, software and verification to develop IP that meets the power,...


  • Sunnyvale, United States META Full time

    The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.ASIC Engineering Manager, Design Verification ResponsibilitiesManage an ASIC design verification...

  • ASIC/RTL Design Engineer

    Found in: Jooble US O C2 - 2 weeks ago


    Santa Clara, CA, United States Saicon Consultants, Inc. Full time

    ASIC/RTL Design Engineer Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural...


  • San Jose, CA, United States Recogni Full time

    About Recogni: Artificial intelligence (AI) is transforming our world. It can perform cognitive functions that previously only humans could do, such as perceiving interactions across different environments with the ability to quickly learn and then solve complex problems. Recogni is a system solution company that specializes in the design of...

  • Sr.-Principal ASIC Design Engineer

    Found in: Jooble US O C2 - 2 weeks ago


    San Jose, CA, United States Tripod Networking Full time

    Location: San Jose, CA or Remote Will transfer H1's. Will consider relocation if needed. Responsibilities: Micro-architecture specifications and participate in specification and test plan reviews. Architect and implement complex RTL designs. Integrate CPU and other relevant IPs into the CPU sub-system. Work with the physical design team to...

  • Physical Design Flow and Methodology Engineer

    Found in: Careerbuilder One Red US C2 - 24 hours ago


    Sunnyvale, CA, US Google Full time

    Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 10 years of experience with EDA tool workflows in semiconductor environments. Experience developing and supporting ASIC physical design flows and methodologies in process nodes. Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow...