Sr. SOC/ASIC Physical Verification Engineer

The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.ASIC Engineering Manager, Design Verification ResponsibilitiesManage an ASIC design verification...

The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. ASIC Engineering Manager, Design Verification Responsibilities Manage an ASIC design...

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC PHYSICAL DESIGN STA/TIMING ENGINEER (SILICON ENGINEERING) At...

As a ASIC Physical Implementation, Principal Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies...

Job Responsibilities •To help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture •Participating in Architecture definition and modeling, micro-architecture review. •Developing the verification and emulation environment, chip and block level test plan, post-silicon bring-up scripts and plan. •Collaborate...

Job Title: Design Verification Engineer Duration: 12 mos + Possible extension Location: : Sunnyvale CADescription:•Strong DV background (test plan development, test writing, SystemVerilog, UVM)Duties: Write and augment existing testplans. Implement testbench and scoreboards / checkers. Implement test sequences as per plan and debug failures Achieve 100%...

Excited about working at the core of Alexa devices? Come, join us and build the latest of computer vision, machine learning, security and mobility for the Intelligent Edge devices. The ideal candidate will be technical, creative, a strong communicator, able to orchestrate a multisite development team, and drive solutions in collaboration with teams and...

Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills: UVM and System Verilog Requirement:. • 5+ or more years of proven experience on ASIC / SoC / IP Verification. • Strong experience in SystemVerilog and UVM verification methodologies • Proficiency in...

Company Summary: oneNav is powering high performance positioning for location dependent mobile services. Based in Silicon Valley, oneNav is developing a next generation, pureL5 mobile GNSS receiver for smartphones, wearables and IoT devices. Job Summary: We are seeking a highly skilled and motivated Implementation Engineer with in-depth knowledge of RTL...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience. Digital design experience using SystemVerilog RTL Preferred qualifications: 3 years of experience in digital design using SystemVerilog or RTL. Experience with high-bandwidth bus architectures including control and memory bus...

Location: Austin, TX or Sunnyvale, CAQualification/Experience/Skills Required:10+ years industry experience, BS EE.Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes.Hands-on experience with block level physical design (Floorplanning to GDSII).Experience with SoC level...

Location: Austin, TX or Sunnyvale, CAQualification/Experience/Skills Required:10+ years industry experience, BS EE.Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes.Hands-on experience with block level physical design (Floorplanning to GDSII).Experience with SoC level...

This position requires a highly motivated and experienced person to work with Synopsys’ customers on integrating leading edge Interface IP (IIP) into their ASIC SoC/systems for next generation products. The position offers opportunities to work on SynopsysUCIe (Universal Chiplet Interconnect Express) IPand the latest industry specifications/applications on...

We are seeking a Digital Verification Engineer who will be involved for functional verification of High Speed interface IPs. A dynamic personality with eager to learn, drive Pre-silicon verification activities, good knowledge of digital design & HDL implementation. Job Description Work on Functional Verification of High speed serial link PHY IPs for USBx,...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

Location: Austin, TX or Sunnyvale, CA Qualification/Experience/Skills Required: 10+ years industry experience, BS EE. Hands-on tape-out experience performing timing and physical verification closure on 5nm FinFET TSMC process or similar/lower technology nodes. Hands-on experience with block level physical design (Floorplanning to GDSII). Experience with...

Minimum qualifications: Bachelor's degree in Electrical Engineering or equivalent practical experience. 10 years of experience with EDA tool workflows in semiconductor environments. Experience developing and supporting ASIC physical design flows and methodologies in process nodes. Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow...

Job Description: We are seeking a Sr Algorithm Engineer for a very important client. we are looking for talented team members to help us deliver our advanced computer vision algorithms to tomorrow's intelligent video products Studying industry trends across deep learning and computer vision, we create new ideas and concepts for HDR tone mapping and low...

RTL ASIC Design Engineers with 8 to 15+ years of experience. No of Openings: 2 Sunnyvale, CA Job Description: 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must. Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB...