Sr. Staff ASIC Design Engineer @ Autonomous Driving Technology Leader

4 weeks ago

San Jose CA, United States Recogni Full time

Artificial intelligence (AI) is transforming our world. Recogni is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We are at the leading edge of advancing the latest research and product improvements for Al inference solutions that will make Al even more advantageous for compelling new applications. Recogni is a well funded, fast-paced startup company with headquarters in both San Jose, CA, and Munich, Germany. We also have many talented team members working remotely. We prioritize our employees' well-being and their families, aiming for a healthier, happier life inside and outside work. We value their contributions and offer tailored benefits for health and financial security, catering to different life stages. Our comprehensive benefits and competitive compensation, including flexible spending and Bonusly awards, reflect our commitment to a supportive and inspiring work environment.
Staff Engineer on Recogni's ASIC team, you will be responsible for the microarchitecture and design implementation of a high-performance and low-power convolutional neural network accelerator ASIC that forms the core of the company's flagship perception module product for autonomous driving applications.This ASIC's design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to form an end-to-end vision perception module that achieves record-breaking computational performance at low power.
Your responsibilities will be wide-ranging and run the gamut of microarchitecture design and documentation, Verilog RTL implementation, selecting and integration 3rd-party IP blocks, working closely with design verification engineers, running frontend synthesis and working with a backend team on place-and-route guidance and timing closure.
Collaborate with the physical design team to resolve implementation and timing issues and to optimize power.
Perform diagnostic and post-silicon validation tests, as well as assist with software bring-up in the lab.
10+ years of ASIC design experience with a demonstrable track record of RTL logic design in multi-million gate ASICs with Verilog or System Verilog.
~ Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
~ Hands-on experience in all aspects of the ASIC development process with proficiency in front-end tools and methodologies.
~ Familiarity with low power design. Interest to explore AI architectures for convolution, transformer and other kinds of workloads
~ S. preferred) degree in Electrical or Computer engineering.


Ground floor opportunity with the team; Learning and development opportunities from a highly diverse and talented peer group, including experts in a wide range of fields, from Artificial Intelligence & Computer Vision to Systems & Device Engineering.
Competitive benefits package including Medical, Vision, Dental
Sharp, motivated co-workers in a fun office environment
Employee Stock Purchase Plan
Flexible work hours & generous PTO policy

Quality and excellence count in everything we do.
All qualified applicants will receive consideration for employment without regard to age, color, gender identity or expression, marital status, national origin, disability, protected veteran status, race, religion, pregnancy, sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances.

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