Physical Design Flow and Methodology Engineer

2 weeks ago

Sunnyvale CA US Google Full time

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering or equivalent practical experience.
  • 10 years of experience with EDA tool workflows in semiconductor environments.
  • Experience developing and supporting ASIC physical design flows and methodologies in process nodes.
  • Experience with scripting languages (i.e., Python, Bash, Tcl) for workflow automation and data visualization.
Preferred qualifications:
  • Experience in extraction of ASIC design parameters, QOR metrics, and analyzing trends.
  • Expertise in one or more aspects of physical design implemenation, including 2.5D and 3DIC integration and signoff, IP integration, chip finishing issues.
  • Proficiency in general software engineering principles (data structures, algorithms, profiling, optimization) and object oriented programming languages such as C++.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

You will be a part of the chip implementation team developing flows and methodologies for workflow automation, data management, metric collection, and dashboarding for physical design EDA tools within the Google Compute Engine environment. You will survey industry trends, perform technical evaluations of vendors, provide recommendations, and employ best practices. Your work will streamline ASIC physical design workflows, make our team of physical design engineers more efficient, and help ensure high quality of results for ASIC tapeouts.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

  • Develop, support, and execute implementation flows from RTL through GDS including some or all of the following: synthesis, floorplanning, place and route, power/clock distribution, extraction, static timing analysis, CDC, formal verification, physical verification, and power integrity.
  • Collaborate with chip design teams to implement flows and methodologies to improve Performance, Power and Area (PPA) and Turn-Around-Time (TAT).
  • Perform technical evaluations of EDA tools and provide recommendations.
  • Work with EDA vendors to resolve tool issues and bugs.

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