Design Verification Engineer

1 week ago


San Francisco, California, United States Enfabrica Full time
Revolutionize AI Compute Systems with Enfabrica

Enfabrica is a pioneering company on a mission to transform AI compute systems and infrastructure at scale. We're seeking a talented Design Verification Engineer to join our team and contribute to the development of superior-scaling networking silicon and software.

Key Responsibilities:
  • Collaborate with world-class distributed systems hardware and software architects to transform product vision and behavioral specifications into efficient, comprehensive block-level and top-level tests.
  • Incorporate state-of-the-art verification techniques to efficiently tackle the demanding scale and performance requirements of a functionally complex device.
  • Define and implement infrastructure for effective HW/SW co-simulation.
  • Execute on a verification strategy which ensures that the prototype meets both the device level specifications as well as the system-level requirements.
Requirements:
  • Proven industry experience and successful track record in verifying chip- and block-level RTL designs for high-performance networking or computing chips.
  • Experience with FPGA design flow/verification is a strong plus.
  • Deep experience with full chip verification and infrastructure development.
  • Strong current knowledge of UVM constructs, components, and practices.
  • Expert knowledge of SystemVerilog, as well as Python or other scripting languages.
  • Experience with C/C++ and general software engineering principles is highly desirable.
  • Minimum BSEE/CE + 15 years or MSEE/CE + 10 years experience.
  • Proven track record of design execution and quality on products which have shipped in high-volume.


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