Design Verification Specialist

1 week ago


San Francisco, California, United States Apptad Inc Full time
Job Overview

Apptad Inc is seeking a highly skilled Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for constructing highly scalable, configurable, and reusable DV/Performance verification environments.

Key Responsibilities
  • Rich experience in constructing highly scalability, configurability, and reusability DV/Performance verification environment.
  • Experience in ASIC design/verification related field in IP, Subsystem or SOC level
  • Experience in writing System Verilog and/or System C models for simulation
  • Working experience in writing UVM models, checkers, and stimulus, constructing UVM register models and applying constrained random methodology in UVM test environment and stimulus
  • Compose test plan and validation vectors to ensure functional completeness
  • Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
  • Versatile in any one of the high-level verification flows such as SV,UVM, C++ etc. as well as knowledge of industry standard tools for verification
  • Excellent communication skills (both written and oral)
  • Strong problem-solving skills
Requirements

We are looking for a highly skilled and experienced Design Verification Engineer who can work effectively in a team environment. If you have a strong background in ASIC design/verification and experience in writing System Verilog and/or System C models for simulation, we encourage you to apply.



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