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Design Verification Engineer

2 months ago

San Jose, California, United States LeadStack Inc. Full time
Job Title: Design Verification Engineer

LeadStack Inc. is a leading provider of contingent workforce solutions, partnering with top Fortune 500 brands. We're seeking a skilled Design Verification Engineer to join our team.

Job Summary

We're looking for a highly experienced Verification Engineer to lead the design verification strategy for complex System IP designs. The ideal candidate will have a deep understanding of constrained randomization, efficient test suites, and experience with System Verilog and UVM.

Key Responsibilities
  • Develop feature-based test plans and UVM sequences, tests, scoreboards, monitors, and checkers.
  • Work with the DV team and designers to build verification environments and write SVA assertions.
  • Regression triaging and debug, with a focus on functional and code coverage closure.
  • Agility to work on multiple tasks and projects, with good communication skills and a team player attitude.
Requirements
  • BS/MS/PhD (or equivalent experience) in a relevant field.
  • 12+ years of relevant experience in Verification, with a focus on System IP designs.
  • Experience with System Verilog, UVM, and constrained randomization.
  • Proficient in a script language like Perl or Python, and working knowledge of C++.
  • Good knowledge of memory subsystems, including interconnect, last-level cache, and coherency.
  • Familiarity with Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols.
  • Experience with Chip2Chip, Die2Die protocols like UCI-E, C2C preferred.

If you're a motivated and experienced Verification Engineer looking for a new challenge, please share your updated resume and we'll be in touch to discuss further.