Design Verification Engineer

1 day ago


San Jose, California, United States Kaygen Full time
Design Verification Engineer

Kaygen is a leading provider of top talent for technology-based staffing services. We specialize in delivering high-volume contingent staffing, direct hire staffing, and project-based solutions to companies worldwide.

Job Title: Design Verification Engineer

Location: Bay Area (Mountain View or San Jose, CA)

Duration: Full-time

Job Description:

We are seeking a skilled Design Verification Engineer to join our team. As a Design Verification Engineer, you will be responsible for architecting and verifying block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces.

Key Responsibilities:

  • Develop test plans and coverage metrics from specifications and write block and chip-level tests in C, SV, and UVM
  • Debug RTL and gate simulations and work with design engineers to verify fixes
  • Replicate silicon bugs in simulation environments and validate fixes or SW workarounds
  • Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup
  • Evaluate latest verification methodologies and develop scripts to automate verification flows

Requirements:

  • UVM, System Verilog, SVA experience
  • Strong understanding of SOCs, PCIe, and High Bandwidth memory
  • Emulation experience with Zebu or Palladium
  • Excellent problem-solving and communication skills

What We Offer:

  • Free health insurance
  • PTOs: 10 business days (including sick leaves)
  • 401(k) Retirement Plan
  • Free Life Insurance

About Kaygen:

Kaygen is a team-oriented company that values respect, honesty, and integrity. We strive to provide our employees with a dynamic and supportive work environment. If you are a motivated and experienced individual looking for a new challenge, we invite you to join our team of talented IT professionals.



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