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Design Verification Engineer

2 months ago


San Jose, California, United States LeadStack Inc. Full time
Job Title: Design Verification Engineer

LeadStack Inc. is a leading provider of contingent workforce solutions, partnering with top Fortune 500 brands. We're seeking a skilled Design Verification Engineer to join our team.

Job Summary:

We're looking for a highly experienced Design Verification Engineer to lead the functional verification strategy of complex System IP designs. The ideal candidate will have a deep understanding of constrained randomization, efficient test suites, and experience with System Verilog and UVM.

Key Responsibilities:
  • Develop feature-based test plans and execute functional verification strategies
  • Work with the DV team and designers to build verification environments
  • Develop UVM sequences, tests, scoreboards, monitors, and checkers
  • Write SVA assertions and achieve functional and code coverage closure
  • Regression triaging and debug
  • Agility to work on multiple tasks and projects
Requirements:
  • BS/MS/PhD in Computer Science or related field
  • 12+ years of relevant experience in Verification
  • Experience with System Verilog and UVM
  • Deep understanding of constrained randomization and efficient test suites
  • Proficient in a script language like Perl or Python
  • Working knowledge of C++
  • Good knowledge of memory subsystem, including interconnect, last-level cache, coherency
  • Familiarity with Arm AMBA5 CHI, AMBA4 ACE, or AXI coherent interconnect and bus protocols
  • Experience with Chip2Chip, Die2Die protocols like UCI-E, C2C preferred
  • Good communication skills and ability to work as a team player

If you're a motivated and experienced Design Verification Engineer looking for a new challenge, please share your updated resume and we'll be in touch to discuss further.