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Lead DV IP Verification Engineer

2 months ago

California, United States Capgemini Engineering Full time
About the Role

We are seeking a highly skilled Verification Expert to join our team at Capgemini Engineering. As a key member of our team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.

Key Responsibilities
  • Design and develop verification environments using System-Verilog and UVM
  • Collaborate with cross-functional teams to ensure seamless integration of verification environments
  • Develop and maintain high-quality verification plans, testbenches, and test cases
  • Identify and troubleshoot issues in verification environments
  • Develop and maintain documentation for verification environments and test cases
Requirements
  • Proficiency in System-Verilog and UVM
  • Strong knowledge of verification methodologies and best practices
  • Experience with C/C++ and Python programming languages
  • Excellent problem-solving and analytical skills
  • Strong communication and collaboration skills
About Capgemini Engineering

Capgemini Engineering is a world leader in engineering and R&D services, combining its broad industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds. We help clients accelerate their journey towards Intelligent Industry.

What We Offer
  • A dynamic and collaborative work environment
  • Opportunities for professional growth and development
  • A competitive salary and benefits package
  • A chance to work on exciting and challenging projects