ASIC DFT Hardware Engineer

4 weeks ago


San Jose, California, United States Cisco Full time
About the Role

Cisco is seeking an experienced ASIC DFT Engineer to join our Silicon One development organization in San Jose, CA. As a key member of our team, you will be responsible for implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics needs of our designs.

Key Responsibilities
  • Implement DFT features that support ATE, in-system test, debug, and diagnostics needs of our designs.
  • Develop innovative DFT IP in collaboration with multi-functional teams and play a key role in full chip design integration with testability features coordinated in the RTL.
  • Work closely with design/design-verification and PD teams to enable the integration and validation of test logic in all phases of the implementation and post-silicon validation flows.
  • Participate in the creation of innovative hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die, driving reusable test and debug strategies.
Requirements
  • Bachelor's or Master's Degree in Electrical or Computer Engineering with at least 10 years of good experience in latest innovative trends in DFT, test, and silicon engineering.
  • Good experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
  • Good experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime.
  • Verification skills include System Verilog Logic Equivalency checking and validating the Test-timing of the design.
  • Experience working with Gate level simulation, debugging with VCS and other simulators.
  • Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687.
  • Strong verbal skills and ability to thrive in a multifaceted environment.
  • Scripting skills: Tcl, Python/Perl.
Preferred Skills
  • Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification.
  • DFT CAD development - Test Architecture, Methodology, and Infrastructure.
  • Test Static Timing Analysis.
  • Post-silicon validation using DFT patterns.

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