Senior ASIC Implementation Engineer
4 weeks ago
As a member of the Silicon One development organization, you will be responsible for driving DFT requirements early in the design cycle. You will work closely with Front-end RTL teams and backend physical design teams to understand chip architecture and craft groundbreaking next generation networking chips. Your primary focus will be on Design-for-Test, and you will help lead the DFT and quality process through the entire Implementation flow and post silicon validation phases.
Key Responsibilities:
- Work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle.
- Craft groundbreaking next generation networking chips.
- Help lead the DFT and quality process through the entire Implementation flow and post silicon validation phases.
Requirements:
- BS/MS in Electrical Engineering or Computer Science.
- 7+ year minimum of hands-on experience in ASIC implementation and Physical verification.
- Prior experience in one of the scripting languages (Python, Tcl, Skill).
- Prior experience working with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical design teams.
- 7+ years of experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support.
- Previous work experience working with Package and floorplan teams to define padring and bump-map design.
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