High-Performance ASIC Design Expert
6 days ago
Estimated salary: $180,000 - $250,000 per year
About the RoleWe are seeking an experienced ASIC Design for Test Engineer to join our team at Cisco's Milpitas/San Jose office location. The ideal candidate will have a strong background in hardware design-for-test (DFT) and be able to implement innovative DFT features that support ATE, in-system test, debug, and diagnostics needs of designs.
Key Responsibilities- Design and develop DFT logic and IP integration using Verilog
- Collaborate with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle
- Work closely with design/design-verification and PD teams to enable integration and validation of test logic in all phases of implementation and post-silicon validation flows
- Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 6 years of experience
- Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
- Prior experience working with Gate level simulation, debugging with VCS and other simulators
- Prior experience with Post-silicon validation and debug experience; ability to work with ATE patterns, P1687
- Prior experience with Scripting skills: Tcl, Python/Perl
Cisco is a leading networking company that connects everything: people, processes, data, and things. We innovate everywhere, taking bold risks to shape the technologies that give us smart cities, connected cars, and handheld hospitals. At Cisco, we celebrate creativity and diversity, and we're committed to making a positive impact on society.
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