IP Design Verification Engineer

2 days ago


California, United States Capgemini Engineering Full time
Job Summary

Capgemini Engineering is seeking a highly skilled IP Design Verification Engineer to join our team. As a key member of our engineering team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.

Key Responsibilities
  • Design and develop verification environments using System-Verilog and UVM
  • Collaborate with cross-functional teams to ensure seamless integration of IP and SoC verification
  • Develop and maintain high-quality verification environments and testbenches
  • Conduct thorough analysis and debugging of verification results
  • Stay up-to-date with industry trends and emerging technologies in verification and validation
Requirements
  • Proficiency in System-Verilog and UVM
  • Strong knowledge of verification methodologies and techniques
  • Experience with C/C++ and Python programming languages
  • Excellent problem-solving and analytical skills
  • Strong communication and collaboration skills
About Capgemini Engineering

Capgemini Engineering is a world leader in engineering and R&D services, combining industry knowledge and cutting-edge technologies to support the convergence of the physical and digital worlds. We help clients accelerate their journey towards Intelligent Industry.

As a Capgemini Engineering employee, you will have the opportunity to work on challenging projects, collaborate with talented professionals, and develop your skills and expertise in a dynamic and supportive environment.



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