IP Design Verification Engineer
6 days ago
Capgemini Engineering is seeking a highly skilled Lead DV IP Verification Engineer to join our team. As a key member of our engineering team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification. This role requires strong expertise in UVM, SystemVerilog, and C++/Python programming languages.
Key Responsibilities- Design and develop verification environments using System-Verilog and UVM methodology
- Collaborate with cross-functional teams to ensure seamless integration of IP verification with SoC verification
- Develop and maintain high-quality verification environments, including testbenches and assertions
- Conduct thorough analysis of verification results and identify areas for improvement
- Develop and maintain documentation for verification environments and testbenches
- Strong expertise in UVM, SystemVerilog, and C++/Python programming languages
- Proficiency in design and verification of IP and SoC using System-Verilog and UVM methodology
- Excellent problem-solving and analytical skills
- Strong communication and collaboration skills
- Ability to work in a fast-paced environment and meet deadlines
At Capgemini Engineering, we offer a dynamic and challenging work environment, competitive compensation and benefits, and opportunities for professional growth and development. If you are a motivated and experienced verification engineer looking for a new challenge, please submit your application.
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IP Design Verification Engineer
2 days ago
California, United States Capgemini Engineering Full timeJob SummaryCapgemini Engineering is seeking a highly skilled IP Design Verification Engineer to join our team. As a key member of our engineering team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.Key ResponsibilitiesDesign and develop verification environments...
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IP Design Verification Engineer
2 weeks ago
California, United States Capgemini Engineering Full timeJob OverviewCapgemini Engineering is seeking a highly skilled IP Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.Key ResponsibilitiesDesign and develop verification environments...
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IP Design Verification Engineer
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California, United States Capgemini Engineering Full timeJob SummaryWe are seeking a highly skilled IP Design Verification Engineer to join our team at Capgemini Engineering. As a key member of our verification team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.Key ResponsibilitiesDesign and develop verification...
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IP Design Verification Engineer
1 week ago
California, United States Capgemini Engineering Full timeJob SummaryCapgemini Engineering is seeking a highly skilled IP Design Verification Engineer to join our team. As a key member of our verification team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.Key ResponsibilitiesDesign and develop verification environments...
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IP Design Verification Engineer
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California, United States Capgemini Engineering Full timeJob SummaryWe are seeking a highly skilled Lead DV IP Verification Engineer to join our team at Capgemini Engineering. As a key member of our verification team, you will be responsible for architecting and creating verification environments using System-Verilog and UVM methodology for IP verification.Key ResponsibilitiesDesign and develop verification...
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Lead DV IP Verification Engineer
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