Design Verification Specialist
2 days ago
Tara Technical Solutions (TTS) is seeking a highly skilled Principal ASIC Verification Engineer to join our team in San Jose. This is a full-time position.
Job Summary:
We are looking for an experienced ASIC Verification Engineer to develop and implement advanced verification components, including UVM agents and behavioral models, using modern verification techniques. The ideal candidate will have a strong background in RTL verification methodologies, including System Verilog, and experience with hardware design and debug.
Key Responsibilities:
- Develop and implement advanced verification components, including UVM agents and behavioral models, using modern verification techniques.
- Design and implement coverage and assertions using System Verilog.
- Develop random and directed test cases against the specification.
- Collaborate with cross-functional teams to ensure successful project delivery.
- Stay up-to-date with industry trends and emerging technologies.
Requirements:
- Experience in verifying designs at system level and block level.
- Fluent knowledge of RTL verification methodologies, including System Verilog.
- Strong experience in ASIC design verification flows and DV methodologies.
- Strong working knowledge of object-oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting skills.
- Experience with hardware design and debug, C++/SystemC, and other programming languages are a strong plus.
- Experience working with emulators and FPGA-based prototyping is a plus.
- Familiarity with overall chip design methodologies and tools.
- Knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design is preferred.
What We Offer:
Tara Technical Solutions (TTS) offers a competitive salary and benefits package, as well as opportunities for professional growth and development.
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