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Senior ASIC Timing Engineer

2 months ago

Santa Clara, California, United States NVIDIA Full time
About the Role

NVIDIA is seeking a highly skilled Senior ASIC Timing Engineer to join our Advanced Technology Group. As a key member of our team, you will be responsible for optimizing design tradeoffs and methodology on next-generation CMOS technology.

Key Responsibilities
  • Develop and implement timing analysis and closure strategies for complex ASIC designs
  • Collaborate with place and route teams to understand and implement constraints
  • Find the right balance between frequency, power, area, congestion, and yield
  • Work on all aspects of DFT/Test timing, including timing constraints, analysis, convergence, and ECO implementation
Requirements
  • BS in Electrical or Computer Engineering or equivalent experience
  • 5 years of experience in physical design and timing
  • Expertise in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence
  • Hands-on knowledge of industry-standard Timing/STA EDA tools
  • Proficiency in programming and scripting languages, such as TCL and Python
Preferred Qualifications
  • Experience with DFT timing closure for various modes
  • Knowledge of clocking and clock controls in DFT modes
  • Experience in methodology or flow development
About NVIDIA

NVIDIA is a leader in the technology industry, known for its innovative products and commitment to diversity and inclusion. We offer a competitive salary range of $128,000 - $258,750, as well as equity and benefits.