ASIC Design Verification Engineer

7 days ago

Washington, Washington, D.C., United States META Full time
Job Summary

Meta is seeking a highly skilled ASIC Design Verification Engineer to join our Infrastructure organization. As a key member of our team, you will be responsible for the verification closure of design modules or sub-systems from test-planning to verification closure. You will work closely with cross-functional teams to develop innovative ASIC solutions for Meta's data center applications.

Key Responsibilities
  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification.
  • Develop functional tests based on verification test plan.
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
  • 5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
  • Track record of 'first-pass success' in ASIC development cycles.
  • 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Preferred Qualifications
  • Experience in development of UVM based verification environments from scratch.
  • Experience verifying GPU/CPU designs.
  • Experience with micro-architectural performance verification.
  • Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
  • Experience with verification of ARM/RISC-V based sub-systems or SoCs.
  • Experience with IP or integration verification of high-speed interfaces like PCIe, RoCE, DDR, HBM, Ethernet.
  • Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
  • Experience working across and building relationships with cross-functional design, model and emulation teams.
  • Experience with revision control systems like Mercurial(Hg), Git or SVN.
Compensation

$142,000/year to $203,000/year + bonus + equity + benefits

About Meta

Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.

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