Synthesis Engineer

7 days ago


Austin, Texas, United States Apple Full time
About the Role

We are seeking a highly skilled Synthesis Engineer to join our team at Apple. As a key member of our hardware engineering team, you will be responsible for optimizing designs to achieve groundbreaking power, area, and timing goals.

Key Responsibilities
  • Deliver timing-clean, logically equivalent netlists to the physical design team.
  • Collaborate with functional teams to continually question the limitations of technology.
  • Optimize designs for best-in-class low power and high performance with logically equivalent RTL transforms.
  • Implement ECOs (Engineering Change Orders) for functional and timing closure.
  • Work closely with the Design Verification (DV) team to ensure design quality.
Requirements
  • Professional experience with STA (static timing analysis), Verilog/VHDL, and Synthesis.
  • Deep understanding of physical design concepts/constraints, including floor-planning, placement, congestion, and setup/hold timing closure.
  • Ability to collaborate effectively with different functional teams and strong written/verbal communication skills.
  • Experience with multi-clock and multi-power domain designs.
  • Familiarity with DFT (Design for Testability) insertion and multi-mode timing constraints.
Preferred Qualifications
  • Bachelor's Degree + 10 years of experience.
About Apple

Apple is an equal opportunity employer committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.



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