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Senior ASIC Design Engineer
2 months ago
We are seeking a highly skilled Senior ASIC Design Engineer to join our Cloud-Scale Machine Learning Acceleration team at Amazon. As a key member of our team, you will be responsible for designing and optimizing hardware in our data centers, including our custom-designed machine learning inference datacenter server, AWS Inferentia.
Key Responsibilities- Integrate multiple subsystems into a top-level SOC, ensuring correct clock/reset/functional/DFT signal routing.
- Implement and deliver high-performance, area, and power-efficient RTL to achieve design targets and specifications.
- Analyze design, microarchitecture, or architecture to make trade-offs based on features, power, performance, or area requirements.
- Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
- Perform lint and clock domain crossing quality checks on the design.
- Work with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing, and back-end teams to accomplish tasks.
- B.S. in Electrical Engineering or related technical field.
- 5+ years of experience in RTL design for SOC.
- 5+ years of experience in VLSI engineering.
- 5+ years of experience with code quality tools, including Spyglass, LINT, or CDC.
- Master's degree in electrical engineering, computer engineering, or equivalent.
- Experience with microarchitecture, SystemVerilog RTL, assertions, SDC constraints.
- Experience with automation and scripting languages, such as Python.
- Familiarity with data path design, interconnects, AXI protocol.
- Good analytical, problem-solving, and communication skills.
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