Senior Principal Engineer
1 day ago
Cadence Design Systems is a global leader in electronic design automation, and we're seeking a highly skilled Senior Principal Engineer to join our team. As a key member of our development team, you'll have the opportunity to design and develop state-of-the-art DDR memory controllers for a wide range of applications, including datacenter, edge computing, automotive, and AI.
Responsibilities:- Develop and improve highly automated and customizable synthesis design flows for highly configurable designs using modern methodologies.
- Develop and recommend better design method practices to enable better synthesis convergence.
- Collaborate closely with the ASIC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs.
- Resolve design/timing/congestion and flow issues, identify potential solutions, and drive execution.
- Run, debug, and fix signoff closure issues in static timing analysis (STA).
- Ensure full chip and block-level timing constraints for area and timing optimization.
- BS in Electrical, Computer Engineering, or equivalent experience with 7+ years of ASIC and/or physical design flow experience; MS preferred.
- Familiarity with Verilog and ASIC design, along with experience in commercial EDA tools (Lint, Physical Synthesis, CDC, LEC, Formal).
- Strong proficiency in at least one of Python, Perl, Tcl, or C/C++.
- Experience with logic synthesis, physical design, formal equivalence checking.
- Scripting experience with Python, Tcl, or Perl.
Cadence Design Systems is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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