Senior ASIC Design Engineer
2 hours ago
Job Summary:
Meta is seeking a highly skilled ASIC Design Engineer to join our Infrastructure organization. The successful candidate will be responsible for designing cutting-edge machine learning ASICs, capable of world-class inference and training performance.
Key Responsibilities:
- Develop micro-architecture for complex SoC and IP.
- Design and develop RTL using Verilog, System Verilog, and HLS.
- Collaborate with verification and emulation teams in test plan development and debug.
- Collaborate with implementation team to close the design on timing and power.
Requirements:
- 3+ years of silicon development experience.
- Experience with Verilog or System Verilog.
- Experience in one of the following skills: micro-architecture and RTL development for complex control and data path IPs, SoC micro-architecture, design, and integration, or implementation and power methodology development.
- Currently pursuing or has a Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field.
Preferred Qualifications:
- Experience in data path development.
- Experience with synthesis and timing closure.
Compensation:
$106,000/year to $166,000/year + bonus + equity + benefits
Industry:
Internet
Equal Opportunity:
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based on race, religion, color, national origin, sex, sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.
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