ASIC Design Verification Engineer
2 weeks ago
We are seeking a highly skilled ASIC Design Verification Engineer to join our team at Meta. As a key member of our Infrastructure organization, you will be responsible for developing innovative ASIC solutions for our data center applications.
Key Responsibilities:- Develop functional tests based on verification test plans.
- Drive Design Verification to closure based on defined verification metrics.
- Debug, root-cause, and resolve functional failures in the design.
- Collaborate with cross-functional teams to ensure the highest design quality.
- Currently pursuing or has a Bachelor's degree in Computer Science, Computer Engineering, or relevant technical field.
- Hands-on experience with constrained-random, coverage-driven verification, or C/C++ verification.
- Experience in verifying IP blocks using standard DV-based techniques.
- Proficiency in EDA tools and scripting languages (Python, TCL, Perl, Shell).
- Experience in developing SV/UVM-based verification environments from scratch.
- Experience debugging fails to the line of RTL, closing out bug fixes.
- Experience with revision control systems like Mercurial, Git, or SVN.
- Experience working in a CPU/GPU environment.
$95,400/year to $133,000/year + bonus + equity + benefits
Industry:Internet
Equal Opportunity:Meta is an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based on race, religion, color, national origin, sex, sexual orientation, gender, gender identity, or other protected characteristics.
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