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Senior ASIC Timing Engineer

2 months ago

Santa Clara, California, United States NVIDIA Full time
About NVIDIA

NVIDIA is a pioneering technology company that has consistently pushed the boundaries of innovation over the past two decades. Our groundbreaking invention of the GPU in 1999 revolutionized the PC gaming market, redefined modern computer graphics, and transformed parallel computing. More recently, our GPU deep learning technology has ignited the modern AI era, marking a new frontier in computing.

Job Summary

We are seeking a highly skilled ASIC Timing Engineer to join our dynamic and growing team. As a key member of our organization, you will play a critical role in driving timing analysis and closure of our GPUs, CPUs, DPUs, and SoCs at the block, cluster, and full-chip levels.

Key Responsibilities
  • Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs, and SoCs at block level, cluster level, and/or full chip level.
  • Collaborate with PD, DFX, Clocks, and other teams to develop timing closure strategies, create timing constraints, drive timing and power convergence, and implement ECOs.
  • Apply knowledge and experience to improve timing convergence flows, working closely with methodology teams.
Requirements
  • BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience or MS (or equivalent experience) with 2+ years of experience in Timing and STA.
  • Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation and management.
  • Expertise in analysis and fixing of timing paths through ECOs, including crosstalk and noise analysis.
  • Expertise and in-depth knowledge of industry-standard STA and timing convergence tools.
  • Knowledge of deep sub-micron process nodes and hands-on experience in modeling and converging timing in these nodes.
Preferred Qualifications
  • Background in domain-specific STA and timing convergence, such as GPUs, CPUs, DPUs/Network processors, or SoCs.
  • Understanding of DFT logic and experience with DFT timing closure for various modes, e.g., scan, BIST, etc.
  • Understanding and timing closure of digital logic/macros in AMS designs/IPs.
  • Experience in methodology and/or flow development as well as automation.
About the Role

NVIDIA is widely recognized as a leader in AI computing and is one of the most desirable employers in the technology industry. We have a talented and dedicated team of individuals who are passionate about innovation and excellence. If you are a creative and autonomous professional looking for a challenging and rewarding opportunity, we encourage you to apply.

The base salary range for this position is $128,000 - $258,750. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. You will also be eligible for equity and benefits.

NVIDIA is committed to fostering a diverse and inclusive work environment and is an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.