Senior UVM Design Verification Engineer
5 days ago
We are seeking a highly skilled and motivated Design Verification Engineer to join our team at AMD. As a key member of our Verification Engineering team, you will be responsible for developing and maintaining tests for functional verification and performance verification at the IP level.
The PersonYou will be a team player with excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You will have strong analytical and problem-solving skills and be willing to learn and ready to take on problems.
Key Responsibilities- Develop/Maintain tests for functional verification and performance verification at the IP level
- Build testbench components like drivers, monitors, checkers to verify next generation IP
- Maintain or improve existing tests to support IP level testing
- Triage regression results and debug failures
- Analyze coverage data to drive stimulus quality
Must have proven number of years industry experience in UVM. Strong at System Verilog, UVM based testbench coding. Experience with functional verification of design IPs. Strong Knowledge of computer architecture. Good ability to write scripts in Perl/Python to enable automation. Any experience with protocols like PCIe, CXL, NVMe is an advantage.
Academic CredentialsBachelors or Masters degree in computer engineering/Electrical Engineering
LocationSan Jose, CA
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