Senior Verification Application Engineer

3 weeks ago


San Jose, California, United States Cadence Design Systems Full time
Key Responsibilities:
  • Establish technical credibility and rapport with customers
  • Provide in-depth technical assistance to support advanced verification flows
  • Champion customer needs and develop competitive technical solutions
  • Understand the competitive landscape and differentiate Cadence solutions
  • Write technical product literature and review new product proposals
Requirements:
  • 5+ years experience with SystemVerilog, VHDL, Verilog
  • BS, MS, or PhD degree in Computer Science/Engineering, Electrical Engineering, or related field
  • Verification skills such as UVM testbench architecture, development, and debug
  • Strong RTL and Testbench debug skills
  • Experience in writing scripts (Perl, Python, or Tcl)
Preferred Qualifications:
  • Experience with C/C++/SystemC
  • Experience in deploying VIP in testbenches
  • Knowledge of protocols like JTAG, UART, PCIe, AMBA, DDR
  • Knowledge of design fundamentals such as architecture, micro-architecture, HDLs, and Synthesis and timing
  • Digital design experience
Benefits:
  • Competitive salary range: $138,600 to $257,400
  • Eligible for bonus, equity, and benefits
  • 401(k) plan with employer match
  • Employee stock purchase plan
  • Medical, dental, and vision plan options


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