Senior Principal DFT Architect

1 day ago


Santa Cruz, California, United States ZipRecruiter Full time
Job Overview

At ZipRecruiter, we're seeking a highly skilled Senior Principal DFT Architect to join our team. As a key member of our Design for Test (DFT) team, you will be responsible for implementing and validating innovative DFT techniques for complex System-on-Chip (SoC) designs.

Responsibilities
  • Architect and implement DFT solutions for SoCs catering to multiple business lines.
  • Coordinate DFT requirements across SoC, IP, and product teams.
  • Develop and validate DFT logic for SoCs and sub-systems using industry-standard simulation tools.
  • Work closely with multi-functional teams to support DFT RTL level insertion, synthesis, and scan insertion, place-and-route, and static-timing-analysis and timing closure.
  • Participate in Automated Test Equipment (ATE) targeted test patterns, validation, and silicon-debug.
  • Collaborate with Test and product engineering teams on silicon characterization and validation.
Requirements
  • 16+ years of proven experience in Design for Test.
  • 10+ years of experience handling DFT architecture for complex SoCs in leading technology nodes.
  • Core DFT skills considered crucial for this position include:
    • Siemens DFT tools
    • Streaming Scan Network (SSN)
    • Scan compression and insertion
    • Memory BIST and repair scheme implementation
    • Logic BIST
    • JTAG/IJTAG
    • At-speed test
    • ATPG
    • Fault simulation
    • DFT mode timing constraints
    • Back-annotated gate level verification
    • Silicon debug
    • Memory and scan diagnostics
  • Experience with 2.5D and 3D test.
  • Experience coding Verilog RTL, TCL, and/or Perl.
Preferred Skills
  • Familiarity with SoC style architectures, including multi-clock domain and low power design practices.
  • Previous experience managing a team of DFT Engineers.
  • Familiarity with Arm IP, including Cortex CPUs, Mali GPUs, AMBA protocols, CoreLink interconnects, and CoreSight debug.
  • Background in design, implementation, and timing convergence.
  • Experience in leading datacenter SoCs.
  • Experience with Cadence and/or Synopsys DFT and simulation tools.


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