ASIC Engineer, Power

JOB TITLE: ASIC Power Engineer LOCATION: Onsite in Sunnyvale, CA DURATION: 6 month contract PAY RANGE: $94 - $104/hour TOP 3 SKILLS: Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules) Should know how to use Python, Perl (or similar) scripting and data-post-processing tools Experience in low power design, tools and...

JOB TITLE: ASIC Power Engineer LOCATION: Onsite in Sunnyvale, CA DURATION: 6 month contract PAY RANGE: $94 - $104/hour TOP 3 SKILLS: Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules) Should know how to use Python, Perl (or similar) scripting and data-post-processing tools Experience in low power design, tools and...

Job Description: Must be available to work onsite in Sunnyvale, CA Role: ASIC Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ASIC for Metas AR/VR products. Areas of interests include Graphics or Machine Learning. Primary languages are Python, tcl and SystemVerilog. RESPONSIBILITIES Perform RTL and netlist...

Job Description: Must be available to work onsite in Sunnyvale, CA Role: ASIC Power Engineer DUTIES ASIC Power Engineer to perform power analysis and optimizations in ASIC for Metas AR/VR products. Areas of interests include Graphics or Machine Learning. Primary languages are Python, tcl and SystemVerilog. RESPONSIBILITIES Perform RTL and netlist level Power...

Summary: Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center...

Summary:Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center...

Summary: Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center...

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL ASIC ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging...

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL ASIC ENGINEER (SILICON ENGINEERING) At SpaceX we’re leveraging...

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, Implementation...

Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, Implementation...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

ENGINEERING- Juniper Networks in Sunnyvale, CA seeks ASIC Engineer: Define, architect, code, and deliver complex digital designs and verification suites/tests for ASICs. Develop block level verification environment using Universal Verification Methodology (UVM) and System Verilog. Part-time telecommuting allowed. $184,000/yr. - $211,200/yr. Email res (must...

Summary: ASIC Power Engineer to perform power analysis and optimizations in ASIC for AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, TCL and System Verilog. Responsibilities: Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on...

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center...

Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge ASICs in fields such as machine learning, video transcoding and network acceleration. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center...

8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...

8+years of hands-on Verilog programming experience for ASIC, with proficiency in front-end Cadence tools and methodologies, along with a demonstrable track record of delivering complex RTL logic designs for multi-million gate high speed processors/ASICs. Knowledge of high speed compute (e.g. floating point vector processing units (VPU), GPU shader hardware...