Principal ASIC Engineer

Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer,...

Summary: Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center...

ASIC Design Verification Engineer Client Overview Our client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come. Low Latency has become the key enabler for their industry and other real-time application and the...

ASIC Design Verification EngineerClient OverviewOur client is building the first latency optimized SoC for their industry. Using its proven AI accelerator designs, we are targeting best in class latency with order of magnitude improvements for years to come. Low Latency has become the key enabler for their industry and other real-time application and the...

Summary: Meta is hiring ASIC Power Engineers within our Infrastructure organization to work on low level power designs. We are looking for individuals with experience in power modeling for ASICs (architecture to silicon), developing flows around EDA tools, and low-power design to build efficient System on Chip (SoC) and IP for data center...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

RTL ASIC Design Engineers with 8 to 15+ years of experience.No of Openings: 2 Sunnyvale, CAJob Description:· 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must.· Expertise in Verilog & System Verilog is a must.· Experience in Synthesis / Understanding of timing concepts for ASIC is required.· Experience in design of DDR / USB...

The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. ASIC Engineering Manager, Design Verification Responsibilities Manage an ASIC design...

The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. ASIC Engineering Manager, Design Verification Responsibilities Manage an ASIC design...

Reality Labs focuses on delivering Meta's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Reality Labs Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed...

Summary: The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. Required Skills: ASIC Engineering Manager, Design Verification...

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a ASIC EngineerJob Description:Job Title: ASIC Engineer As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data...

Maxonic maintains a close and long-term relationship with our direct client. In support of their needs, we are looking for a ASIC EngineerJob Description:Job Title: ASIC Engineer As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook's data...

Summary: The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems. Required Skills: ASIC Engineering Manager, Design Verification...

Summary: Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on...

Summary: Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on...

Role ASIC Formal Verification Engineer Location Sunnyvale, CA (Onsite) Client: LTTS/Meta Full Time Only ASIC Engineer, Formal Verification Responsibilities Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level Work...

Role ASIC Formal Verification Engineer Location Sunnyvale, CA (Onsite) Client: LTTS/Meta Full Time Only ASIC Engineer, Formal Verification Responsibilities Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block...

Role ASIC Formal Verification Engineer Location Sunnyvale, CA (Onsite) Client: LTTS/Meta Full Time Only ASIC Engineer, Formal Verification Responsibilities Provide technical leadership in Formal Verification Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block...