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Silicon DV Engineer

2 months ago

Sunnyvale, United States Fresh Consulting Full time

Title: Silicon DV Engineer Duration: 1 year with possible extension Location: Onsite Sunnyvale, CA Benefits: Employee benefits at 100% including Medical, PTO, Holiday Pay, 401K Plan, and much more Hours: Minimum 40 Hours/Week Role:

Responsible for low-power verification including both dynamic and static verification. Write and augment existing test plans. Implement testbench and scoreboards/checkers. Implement test sequences as per plan and debug failures. Achieve 100% functional, code, and power coverage. Work closely with designers, micro architects & firmware engineers to resolve issues. Ability to communicate & articulate clearly progress/issues with project leads. Skills:

7+ years of proven experience as a DV engineer. Hands-on experience with executable test plans and Coverage Driven verification. Hands-on experience with SV (System Verilog) and UVM (Universal Verification Methodology). Hands-on experience with Synopsys VCS / Verdi or Cadence Incisive tools. Experience with UPF-based simulation flow. 2+ Years of experience with C/C++. Preferred Skills:

Power and performance FPGA validation. Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python. Experience with Power-Aware GLS flow. TCL and Python (or similar) scripting language. ASIC design experience. Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators. Experience with complex SoCs. Knowledge of coverage merging across simulation and formal. MSEE/CS or equivalent experience Education: Bachelor's degree in Electrical/Computer Engineering or Computer Science.

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