Current jobs related to Silicon Design verification IV - Sunnyvale - Intelliswift Software

  • Silicon Verification Engineer

    2 weeks ago

    Sunnyvale, California, United States Mindlance Full time

    Job Title: Silicon Verification EngineerWe are seeking a highly skilled Silicon Verification Engineer to join our team at Mindlance. As a key member of our verification team, you will be responsible for designing and implementing verification plans, testbenches, and scoreboards to ensure the quality and reliability of our silicon IPs.Key...

  • Silicon DV Engineer IV

    2 weeks ago

    Sunnyvale, California, United States Ursus Inc Full time

    Job Title: Silicon DV Engineer IVWe are seeking a highly skilled Silicon DV Engineer IV to join our team at Ursus Inc. as a key member of our verification team.Job Summary:The successful candidate will be responsible for low power verification, including both dynamic and static verification. They will write and augment existing test plans, implement...

  • Senior Design Verification Engineer

    1 week ago

    Sunnyvale, California, United States SpaceX Full time

    Job Title: Senior Design Verification EngineerAt SpaceX, we're pushing the boundaries of innovation and technology. As a Senior Design Verification Engineer, you'll play a critical role in developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe.Our team is responsible for designing,...

  • Wireless Design Verification Engineer

    4 weeks ago

    Sunnyvale, California, United States Apple Full time

    Wireless Design Verification EngineerJoin Apple's innovative wireless silicon development team and contribute to the creation of the next generation of wireless silicon. As a Wireless Design Verification Engineer, you will be responsible for the pre-silicon verification of complex high-throughput communication PHY and Radio sub-systems.Key...

  • Senior Design Verification Engineer

    4 weeks ago

    Sunnyvale, California, United States SpaceX Full time

    Job Title: Senior Design Verification EngineerAt SpaceX, we're pushing the boundaries of innovation and technology. We're seeking a highly skilled Senior Design Verification Engineer to join our team and contribute to the development of cutting-edge next-generation FPGAs and ASICs.Responsibilities:Responsible for digital ASIC and/or FPGA verification at...

  • Senior Design Verification Engineer

    4 weeks ago

    Sunnyvale, California, United States SpaceX Full time

    Job Title: Sr. Design Verification EngineerAt SpaceX, we're pushing the boundaries of space technology and exploring new frontiers. As a Sr. Design Verification Engineer, you'll play a critical role in ensuring the quality and reliability of our cutting-edge digital designs.Responsibilities:Develop and execute test plans for digital ASIC and FPGA...

  • Wireless Design Verification Engineer

    4 weeks ago

    Sunnyvale, California, United States Apple Full time

    Job Title: Wireless Design Verification EngineerAre you passionate about wireless communication systems and verification engineering? Do you want to be part of a team that develops cutting-edge wireless silicon technology? We are seeking a highly skilled Wireless Design Verification Engineer to join our team at Apple.Job Summary:We are looking for a talented...

  • Senior Design Verification Engineer

    1 month ago

    Sunnyvale, California, United States SpaceX Full time

    Job Title: Senior Design Verification EngineerAt SpaceX, we're pushing the boundaries of innovation and technology. We're seeking a highly skilled Senior Design Verification Engineer to join our team and contribute to the development of cutting-edge next-generation FPGAs and ASICs.Responsibilities:Develop and execute test plans for digital ASIC and FPGA...

  • ASIC Engineer, Design Verification

    1 month ago

    sunnyvale, United States L&T Technology Services Full time

    Responsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve...

  • ASIC Engineer, Design Verification

    1 week ago

    sunnyvale, United States L&T Technology Services Full time

    Responsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve...

  • ASIC Engineer, Design Verification

    2 months ago

    Sunnyvale, United States L&T Technology Services Full time

    Responsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve...

  • ASIC Engineer, Design Verification

    1 week ago

    Sunnyvale, United States L&T Technology Services Full time

    Responsibilities:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve...

  • ASIC Design Verification Engineer

    4 days ago

    Sunnyvale, California, United States META Full time

    Job Title: ASIC Design Verification EngineerMeta is seeking an experienced ASIC Design Verification Engineer to join our Infrastructure organization. As an ASIC Design Verification Engineer, you will be responsible for developing emulation testbenches in System Verilog and/or C/C++ and delivering emulation and prototyping models from RTL on industry standard...

  • ASIC Engineering Manager, Design Verification Lead

    3 weeks ago

    Sunnyvale, California, United States META Full time

    Job SummaryWe are seeking an experienced ASIC Engineering Manager, Design Verification to lead our design verification team and drive the development of innovative verification methodologies. The ideal candidate will have a strong background in ASIC design verification, management, and leadership experience in small to large size organizations.Key...

  • ASIC Engineering Manager, Design Verification Lead

    1 week ago

    Sunnyvale, California, United States META Full time

    Job Summary:The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.Key Responsibilities:Manage an ASIC design verification team responsible for various...

  • ASIC Engineering Manager, Design Verification Lead

    1 week ago

    Sunnyvale, California, United States META Full time

    Job Summary:The ideal candidate will be a consensus-driven leader with management and leadership experience in small to large size organizations, with comprehensive system and silicon development experience, and a proven track record of first-pass success in ASIC and Systems.Key Responsibilities:Manage an ASIC design verification team responsible for various...

  • Silicon Lifecycle Engineer

    1 week ago

    Sunnyvale, California, United States META Full time

    Job SummaryMeta is seeking a highly skilled Silicon Lifecycle Engineer to join our Infrastructure organization. As a key member of our team, you will be responsible for designing, developing, and validating innovative ASIC solutions for Meta's data center applications.Key Responsibilities Work across all aspects of the silicon lifecycle, from early...

  • Silicon Packaging Design Engineer

    1 week ago

    Sunnyvale, California, United States META Full time

    Job SummaryMeta is seeking an experienced Silicon Packaging Design Engineer to join its Ecosystem and Technical Operation team. The successful candidate will be responsible for designing and developing custom silicon packaging solutions for Meta's infrastructure.The ideal candidate will have a strong background in silicon packaging design, with experience in...

  • Silicon Validation Engineer

    2 months ago

    Sunnyvale, United States Blue Cheetah Analog Design, Inc. Full time

    Silicon Validation Engineer Engineer[On-site Position – Sunnyvale, CA]Blue Cheetah Analog Design Inc. is a semiconductor technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art in package die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high...

  • Silicon Validation Engineer

    1 month ago

    sunnyvale, United States Blue Cheetah Analog Design, Inc. Full time

    Silicon Validation Engineer Engineer[On-site Position – Sunnyvale, CA]Blue Cheetah Analog Design Inc. is a semiconductor technology start-up headquartered in Sunnyvale, California. Our mission is to generate state-of-the-art in package die-to-die semiconductor IP solutions for the rapidly growing chiplet ecosystem. We accomplish this by providing high...

Silicon Design verification IV

4 months ago

Sunnyvale, United States Intelliswift Software Full time

Must Have skills:

• Power and performance modeling or DV (C, system C, system Verilog, or matlab)

• Strong DV background (test plan development, test writing, UVM)

• Experience with low power verification (UPF)

• Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows


Qualifications and Experience:

• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science

• Master's Degree preferred but not required

• 7+ years of proven experience as a DV engineer


“Supplemental” Skills, Plusses:

Power and performance FPGA validation

• Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.

• Experience with Power Aware GLS flow

• Tcl and Python (or similar) scripting language

• ASIC design experience

• Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators

• Experience with complex SoCs

• Knowledge of coverage merging across simulation and formal

• MSEE/CS or equivalent experience


Detailed Job Description

What are the top non-negotiable skill sets required for this role?

• Power and performance modeling or DV (C, system C, system Verilog, or matlab)

• Strong DV background (test plan development, test writing, UVM)

• Experience with low power verification (UPF)

• Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flows

Duties:

• Responsible for low power verification including both dynamic and static verification

• Write and augment existing testplans.

• Implement testbench and scoreboards / checkers.

• Implement test sequences as per plan and debug failures

• Achieve 100% functional, code, and power coverage

• Work closely with designers, micro architects & f/w to resolve issues

• Ability to communicate & articulate clearly progress / issues with project leads

Skills

Must Have:

• 7+ years of proven experience as a DV engineer

o Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification

• Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)

• Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools

• Experience with UPF based simulation flow

• 2+ Years of experience with C/C++

Wish List/ Nice to Have:

• Power and performance FPGA validation

• Hifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.

• Experience with Power Aware GLS flow

• Tcl and Python (or similar) scripting language

• ASIC design experience

• Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators

• Experience with complex SoCs

• Knowledge of coverage merging across simulation and formal

• MSEE/CS or equivalent experience

Education

• Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science

• Master's Degree preferred but not required