Design Verification Engineer

Join to apply for the Design Verification Engineer role at Eridu AI Join to apply for the Design Verification Engineer role at Eridu AI Get AI-powered advice on this job and more exclusive features. This range is provided by Eridu AI. Your actual pay will be based on your skills and experience talk with your recruiter to learn more. Base pay range $190,000.00/yr - $265,000.00/yr Eridu AI is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate training and inference for large-scale AI models. Todays AI performance is frequently limited by system-level bottlenecks. Eridu AI delivers multiple industry-first innovations across semiconductors, software, and systems to unlock greater GPU utilization, reduce capital and power costs, and maximize data center efficiency. The companys solutions and value proposition have been validated by several leading hyperscalers. The company is led by a veteran team of Silicon Valley executives and engineers with decades of experience in state-of-the-art semiconductors, optics, software, and systems, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (Worlds leading micro-LED company and developer of the first augmented reality contact lens). Key Responsibilities Specialized Verification Strategy: Develop verification infrastructure and test cases for ASICs in the area of network fabrics, leveraging your extensive experience in networking. Technical Expertise in ASIC Verification: Provide technical leadership in the verification of complex ASIC designs, ensuring compliance with industry standards and project specifications Gate & Timing simulations: collaborate with the team to execute comprehensive gate-level simulations, including timing and power analysis, to validate the ASIC design before tape-out. RTL Coverage Analysis: deliver detailed coverage metrics to assess the thoroughness of the test suite. Offer actionable feedback to design engineers, focusing on identifying gaps and suggesting enhancements to elevate test effectiveness and broaden coverage scope. Quality Assurance and Process Optimization: Uphold the highest standards of verification quality. Initiate and implement process improvements for increased efficiency and effectiveness. Qualifications ME/BE in Electrical Engineering, Computer Engineering, or related field. Experience: A MINIMUM of 8-15 years in ASIC verification in the area of data center networking. Verification Skills: Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM/VMM/UVM) with a strong understanding of ASIC Design and Verification flow. Experience with functional coverage, gate/timing/power simulations, constrained random verification and test-plan documentation is required. Technical Skills: Python/Perl/Tcl experience, strong problem solving and debugging skill is a plus. Domain Knowledge: Prior experience with Ethernet and PCIe Protocols, Serial and Parallel VIP verification modes and High speed Serdes is a strong plus. Communication Skills: Exceptional communication abilities, capable of effectively coordinating, and articulating complex technical issues in a clear manner. Why Join Us? At Eridu AI, youll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI networking solutions, transforming data center capabilities. The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles. Seniority level Seniority level Mid-Senior level Employment type Employment type Full-time Job function Industries Semiconductor Manufacturing and Computer Hardware Manufacturing Referrals increase your chances of interviewing at Eridu AI by 2x Inferred from the description for this job Medical insurance Vision insurance 401(k) Get notified when a new job is posted. Sign in to set job alerts for Design Verification Engineer roles. San Jose, CA $150,000.00-$230,000.00 1 week ago Sunnyvale, CA $114,000.00-$166,000.00 2 days ago San Jose, CA $136,000.00-$204,000.00 1 week ago Santa Clara, CA $108,000.00-$212,750.00 2 days ago Sunnyvale, CA $114,000.00-$166,000.00 3 weeks ago San Jose, CA $175,000.00-$225,000.00 1 week ago San Jose, CA $180,000.00-$240,000.00 1 week ago Santa Clara, CA $108,000.00-$212,750.00 2 days ago San Jose, CA $160,000.00-$240,000.00 1 week ago Santa Clara, CA $96,000.00-$184,000.00 1 day ago Santa Clara, CA $97,700.00-$182,624.00 6 days ago Sunnyvale, CA $142,000.00-$203,000.00 1 day ago Physical Design and Verification Engineer Sunnyvale, CA $173,000.00-$249,000.00 3 days ago San Jose, CA $130,000.00-$192,000.00 1 week ago Were unlocking community knowledge in a new way. Experts add insights directly into each article, started with the help of AI. #J-18808-Ljbffr