Logic Design and Verification Engineer
3 weeks ago
Tired of working on the same old boring stuff? How about doing something new to change the world? How about working on an exciting next generation of computer memory architecture - Job Description: - Logic design/synthesis/timing analysis or Logic Verification/Test Coverage - Responsible for design or verification, and presentation documents - Requirements: - MS EE/CS or BS EE/CS2 years of experience - Deep knowledge on Computer Architecture especially: out-of-order execution, data hazard, cache/memory subsystems, and simulation tools - Digital system designers: must have experience in design specification, microarchitecture, RTL logic implementation in Verilog/VHDL - Verification engineers: must have experience in advanced verification methodologies such as constrained random test benches, assertion, functional coverage, code coverage and UVM - Team player and an optimist: able to work with teams in multiple office sites. - Plus Skills: - Bus protocol knowledge: ARM AMBA AXI/ACE/CHI or Intel QPI. - Deep knowledge of DDR4, LP4, WIO2, and Cache hierarchy design and optimization of advanced memory controller - Fluent in System Verilog, SVA, C++ or assembly language - Experience with FPGA/emulator (Palladium/Veloce)
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Design Verification Engineer
2 days ago
Santa Clara, United States Talent Software Services, Inc. Full timeDesign Verification Engineer Location: Santa Clara, CA Responsibilities: " Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. " Develop test plans and coverage metrics from specifications and writing block and chip-level...
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Design Verification Engineer
5 days ago
Santa Clara, United States Ampcus Incorporated Full timeRole: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test...
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Design Verification Engineer
1 week ago
Santa Clara, United States Ampcus Full timeRole: Design Verification Engineer Work Location: Santa Clara, CA Background check: Mandatory Meet and great: Mandatory JOB DESCRIPTION: Responsibilities: • Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces. • Develop test plans...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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Design Verification Engineer
3 weeks ago
Santa Clara, United States Mirafra Technologies Full timeLooking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...
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CPU Microarchitecture
1 month ago
Santa Clara, United States Rival Inc Full timePositions are open for full-time in the areas of CPU microarchitecture and logic design, in the areas of memory management, load/store pipeline, cache, power management, debug features, and bus interface designs. We are looking for junior to mid-level of talent, from new college grads to about ten years of experience. Responsibilities Microarchitecture...
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Senior Design Verification Engineer
8 hours ago
Santa Clara, United States NVIDIA Full timeSenior Design Verification Engineer page is loaded Senior Design Verification Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 2 Days Ago job requisition id JR1978941 We are now looking for a Senior Design Verification Engineer! As a member of our CPU Design Verification Team, you will be responsible for a portion of the...
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CPU Microarchitecture
2 weeks ago
Santa Clara, United States Rivos Full timePositions are open for full-time in the areas of CPU microarchitecture and logic design, in the areas of memory management, load/store pipeline, cache, power management, debug features, and bus interface designs. We are looking for junior to mid-level of talent, from new college grads to about ten years of experience. Responsibilities Microarchitecture...
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CPU Microarchitecture
4 weeks ago
Santa Clara, United States Rivos Full timePositions are open for full-time in the areas of CPU microarchitecture and logic design, in the areas of memory management, load/store pipeline, cache, power management, debug features, and bus interface designs. We are looking for junior to mid-level of talent, from new college grads to about ten years of experience. Responsibilities Microarchitecture...
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Silicon Logic Formal Verification
4 weeks ago
Santa Clara, United States Rivos Full timePositions are open for full-time and co-op/internship roles in the areas of formal verification of CPU, Fabric, and Accelerator design **Responsibilities**: - As a Formal Verification Engineer, you will be involved in the formal verification of the architecture and microarchitecture of a high-performance RISC-V core, a coherent fabric, and an accelerator...
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Silicon Logic Formal Verification
3 weeks ago
Santa Clara, United States Rivos Full timePositions are open for full-time and co-op/internship roles in the areas of formal verification of CPU, Fabric, and Accelerator design Responsibilities As a Formal Verification Engineer, you will be involved in the formal verification of the architecture and microarchitecture of a high-performance RISC-V core, a coherent fabric, and an accelerator design. ...
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Staff Engineer
4 hours ago
Santa Clara, United States Marvell Technology Full timeAbout Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new po Verification, Staff, Electrical Engineer, Computer Science, Engineer, Design, Technology, Business Services
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Senior Design Verification Engineer
3 weeks ago
Santa Clara, United States Astera Labs Full timeAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...
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Senior Design Verification Engineer
1 month ago
Santa Clara, United States Astera Labs Full timeAstera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...
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Senior Design Verification Engineer
2 weeks ago
Santa Clara, United States QuEST Global Full timeSenior Design Verification Engineer Santa Clara CA Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. Good knowledge of EDA tools. Experience with signal...
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Senior Design Verification Engineer
1 day ago
Santa Clara, United States QuEST Global Full timeSenior Design Verification Engineer Santa Clara CA Please make an application promptly if you are a good match for this role due to high levels of interest. Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or...
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Senior Design Verification Engineer
2 weeks ago
Santa Clara, United States Quest Global Full timeSenior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...
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Senior Design Verification Engineer
2 weeks ago
Santa Clara, United States Quest Global Full timeSenior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...
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Senior Digital Design Verification Engineer
4 weeks ago
Santa Clara, United States Karkidi Full timeNVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...