Senior Digital Design Verification Engineer

Job DescriptionJob DescriptionResponsibilities:As a Senior Logic Design Engineer, you will be responsible for:Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or...

Senior Design Verification Engineer Santa Clara CA Experience Level: 7-15 years. JOB DESCRIPTION 1 Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc. Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills. Good knowledge of EDA tools. Experience with signal...

Senior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...

Senior Design Verification EngineerSanta Clara CAExperience Level: 7-15 years. JOB DESCRIPTION 1Knowledge of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong HVL (UVM or SystemVerilog with OVM), C/C++, Perl, TCL programming skills.Good knowledge of EDA tools. Experience with signal...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

Silergy Corp, one of the fastest growing analog and mixed-signal semiconductor companies, was founded in Sunnyvale, California by a group of technology innovators and business leaders from Silicon Valley with an average 30 years’ experience. We design and produce innovative mixed-signal and analog ICs that utilize our industry-leading process technologies....

Silergy Corp, one of the fastest growing analog and mixed-signal semiconductor companies, was founded in Sunnyvale, California by a group of technology innovators and business leaders from Silicon Valley with an average 30 years’ experience. We design and produce innovative mixed-signal and analog ICs that utilize our industry-leading process technologies....

Title: RTL Design Engineer - Senior Description: KEY RESPONSIBILITIES: Microarchitecture development of IP subsystems Perform RTL design of digital components. Work with functional verification team to meet coverage and quality sta...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip...

Job Description : We need someone familiar with UVM to run and debug tests. If they are capable, we will also ask them to write some testbench modules and components. Perhaps the most important thing is that they are diligentand good at communicating what they find and where they are. Develop test plans and test benches for module level verification ...

Qualcomm's Power Management Systems team leads the industry in the system architecture and verification of high-performance Power Management Integrated Circuits (PMICs) and Power Management Units (PMUs) embedded in our chipsets for smartphones/tablets, notebooks, automotive infotainment and ADAS system, a variety of cutting-edge consumer electronics...

Qualcomm's Power Management Systems team leads the industry in the system architecture and verification of high-performance Power Management Integrated Circuits (PMICs) and Power Management Units (PMUs) embedded in our chipsets for smartphones/tablets, notebooks, automotive infotainment and ADAS system, a variety of cutting-edge consumer electronics...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

Role/Responsibilities: You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test...

Role/Responsibilities: You will work closely with the design team to define strategy and requirements for block-level and chip-level testing infrastructure. With a thorough understanding of design intent, you will drive the verification environment and the creation of test plans for unit-level and chip-level verification, implement test benches and test...

NVIDIA is seeking hardworking and creative Senior Memory Controller Verification Engineer for our Tegra SoCs! At Nvidia, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the...