Verification Engineer – UVM.
2 days ago
Verification Engineer – UVM
Looking for a solid UVM Verification Engineer.
Scope:
- Ensure shippable first silicon for a company’s first ASIC.
- Develop test benches for blocks & IP.
Required:
- 3+ years of relevant experience developing scalable test benches.
- Solid understanding of System Verilog testbench language.
- Solid with high speed SerDes.
- Comfortable in a fast-paced environment.
- Excited about modern AIs like ChatGPT, & willing to learn about them on the job.
Pluses:
- Experience with chip-to-chip interconnects & HBM3/HBM3E tech.
- Understanding of transformer models & ML.
- Understanding of numerical representations & functions.
- Python programming or other scripting language.
- Understanding of open-source verification tools like Verilator.
Estimated Min Rate: $80.00
Estimated Max Rate: $100.00
Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.#J-18808-Ljbffr
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