Principal Design Verification Engineer
1 day ago
Locations: BANGALORE
Time Type: Full time
Posted on: Posted Yesterday
Job Requisition ID: R46063
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with experience as a design and verification engineer.
- 6+ years of Design Verification experience with SV/UVM.
- Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
- Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
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