Design Verification Engineer
4 weeks ago
Duration: 12 mos + Possible extension
Location: : Sunnyvale CA
Description:
•Strong DV background (test plan development, test writing, SystemVerilog, UVM)
Duties:
- Write and augment existing testplans.
- Implement testbench and scoreboards / checkers.
- Implement test sequences as per plan and debug failures
- Achieve 100% functional, code, and power coverage
- Work closely with designers, micro architects & f/w to resolve issues
- Ability to communicate & articulate clearly progress / issues with project leads
Must Have:
- 7+ years of proven experience as a DV engineer
- Implied: Candidate will have hands on Experience with executable test plans and Coverage Driven verification
- Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
- Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
- Experience with UPF based simulation flow
- 2+ Years of experience with C/C++
- Power and performance FPGA validation
- Experience with Power Aware GLS flow
- Tcl and Python (or similar) scripting language
- ASIC design experience
- Experience with complex SoCs
- MSEE/CS or equivalent experience
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