Senior Design Verification Engineer

5 days ago


Santa Clara, United States Quest Global Full time

Senior Design Verification Engineer

Experience Level: 7-20+ Years

JOB DESCRIPTION 1: Sunnyvale CA

General DV skills, someone who can understand the specs, work with designers, write SV tests, and good at debug. Experience in writing testcase using c/c++ for ARM cores. Debugging test failures in C and SV-UVM mixed environment.

JOB DESCRIPTION 2: Sunnyvale CA

DV background, but more focused or specialized in the python scripting, tool implementation using python, looking for mid/sr level experience.


JOB DESCRIPTION 3: Sunnyvale CA

Proficiency in modern Python (intermediate or above)

Understanding of basic data structures and algorithms

Hands-on experience in SystemVerilog/UVM

Knowledge of UVM RAL (Register Abstraction Layer)

Experience in development in Linux based environments (Bash scripting, Makefile)


Plus:

Experience in development of UVM based verification environments

Experience in EDA tools and scripting used to build tools and flows for verification environments

Experience with revision control systems like Git or Mercurial(Hg)


JOB DESCRIPTION 4: Austin TX, San Jose CA


  1. Very fast paced environment.
  2. Excellent SV/UVM knowledge.
  3. Good to have: LPDDR/DDR protocol knowledge.



  • Santa Clara, CA, United States RF-Design GmbH Full time

    NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...


  • santa clara, United States netPolarity, Inc. (Saicon Consultants, Inc.) Full time

    Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...


  • santa clara, United States netPolarity, Inc. (Saicon Consultants, Inc.) Full time

    Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...


  • Santa Clara, United States netPolarity, Inc. (Saicon Consultants, Inc.) Full time

    Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...


  • Santa Clara, United States netPolarity, Inc. (Saicon Consultants, Inc.) Full time

    Role: Design Verification EngineerLocation: Santa Clara, CA (onsite)Duration: 12 contractJob Description: We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch you as you lead DV teams in new...


  • Santa Clara, United States LanceSoft, Inc. Full time

    Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This...


  • Santa Clara, United States LanceSoft, Inc. Full time

    Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This...


  • Santa Clara, United States LanceSoft, Inc. Full time

    Pay Rate- $90 - $100 hourly on W2Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch...


  • Santa Clara, United States LanceSoft, Inc. Full time

    Pay Rate- $90 - $100 hourly on W2Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch...


  • Santa Clara, California, United States Yoh Full time

    Job Title: Senior PCIe Verification EngineerDescription:We are seeking a highly skilled Senior PCIe Verification Engineer to join our team at Yoh, a Day & Zimmermann company. As a key member of our engineering team, you will be responsible for designing and implementing verification environments for PCIe-based systems.About the Job:This is a contract...


  • Santa Clara County, United States Baya Systems Full time

    Job Title: Senior Hardware Verification Engineer Location: Santa Clara, CAAbout the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our...


  • Santa Clara County, United States Baya Systems Full time

    Job Title: Senior Hardware Verification Engineer Location: Santa Clara, CAAbout the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our...


  • Santa Clara, California, United States Qualcomm Full time

    Job DescriptionWe are seeking a highly skilled and experienced Senior ASIC Design Verification Engineer to lead our design verification team in the development of cutting-edge wireless connectivity products. As a key member of our Engineering Group, you will be responsible for overseeing the entire design verification process, from concept to delivery.About...


  • Santa Clara, United States Mirafra Technologies Full time

    Verification of a new hardware block for dot-product based attentionCreate a constrained-random test suite to test HBM interface performanceCollaborate with the hardware team to root-cause and fix bugs identified during verificationHelp develop a post-silicon validation and bring up strategyHave a deep knowledge of Verilog and UVMHave a bachelor’s degree...


  • santa clara, United States LanceSoft, Inc. Full time

    Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This...


  • santa clara, United States LanceSoft, Inc. Full time

    Pay rate range: $85/hr to $107/hr on W2.Job description:• Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This...


  • santa clara, United States LanceSoft, Inc. Full time

    Pay Rate- $90 - $100 hourly on W2Looking for 8+ years SystemVerilog UVM experience, IP design verification and formal verification.THE ROLE:We are seeking a seasoned verification lead with expertise or significant interest in IO/PHY verification. You have had significant success driving IP verification, UVM and SystemVerilog. This senior role will stretch...


  • Santa Clara, United States Experis Full time

    Our client in the technology industry is seeking a Design Verification Engineer - Specialized to join their team. As a Design Verification Engineer - Specialized, you will be part of the Design Verification team supporting various projects. The ideal candidate will have excellent communication and presentation skills, demonstrated through technical...


  • Santa Clara, United States Manpower Group Inc. Full time

    Our client in the technology industry is seeking a Design Verification Engineer - Specialized to join their team. As a Design Verification Engineer - Specialized, you will be part of the Design Verification team supporting various projects. The ideal candidate will have excellent communication and presentation skills, demonstrated through technical...


  • Santa Clara, United States Acceler8 Talent Full time

    SoC Design Verification EngineerHow has GenerativeAI changed the way data center infrastructure is built and scaled? How can a new interconnect architecture reduce bottlenecks in hyper-distributed systems? If you're passionate about building ground-breaking products to connect and move data across AI infrastructure, this opportunity might be for you!...