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Digital ASIC Verification Lead

3 months ago

North Reading, Massachusetts, United States Teradyne Full time


Press Tab to Move to Skip to Content LinkSelect how often (in days) to receive an alert:Date: May 6, 2024Location: North Reading, MA, USOrganization & Role We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions.

Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively.

Together, Teradyne companies deliver manufacturing automation across industries and applications around the worldTeradynes Silicon Technology Engineering (STE) Digital ASIC Group is responsible for developing advanced node ASICs for Teradynes next-generation products, such as SOC and Memory Test Instruments.

Teradynes products must be ahead of the semiconductor industry for our customers to ship production chips/products.

You will join a best-in-class ASIC team as a Verification Engineer working in collaboration with Digital & Analog designers and product architects to develop Teradynes next-generation large Mixed Signal ASICs.

You will be involved in all phases of development, including specification, architecture, design, verification, and silicon bring-up, focusing on developing UVM-based SystemVerilog Reference Models.


ResponsibilitiesIn this role you will be responsible for:

Leading a team of engineers doing IP, ASIC or FPGA verification Developing verification schedules for complex projectsManaging project execution, from planning to the tapeout sign-offDefining verification strategy and methodologyMentoring junior engineersMaking verification IP selectionsBeing a major contributor Architecting and developing reusable verification environmentsArchitecting and developing reference models for Device Under TestDeveloping detailed executable test plansDeveloping IUVCs, tests, and assertionsPorting tests from simulation to labBasic Qualifications & Skills 15+ years of digital verification experience with a good understanding of digital designProven track record of project execution ownershipExtensive experience modeling Transaction level SystemVerilog Reference ModelsExtensive experience with SystemVerilog programmingExtensive experience with UVM and Coverage Driven MethodologyExperience with Assertion Based VerificationExperience with Cadence tools (Xcelium, vManager) is a plusExperience with gate-level simulations is a plus.

Experience with C/C++ is a plusExperience with PCIe, AXI, LPDDR5 protocols is a plus.
Knowledge of Make, Python, and Regular Expressions is a plus.
Lab validation experience is a plusEducation BS or MSEE#LI-NINJA#LI-ONSITE#J-18808-Ljbffr