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Post Silicon Validation
2 months ago
Mandatory Skills:
Good understanding of processor architecture, Multicore/Multiprocessor with SMP/heterogenous cores.
Good understanding on Cache hierarchy, coherency, and snoop concepts
Good Understanding of CPU Dynamic Frequency and Voltage Switching, Low Power Modes
C language expertise for low level programming, Assembly language for any processor.
Knowledge of Linux kernel internals (process scheduler, memory management, concurrency / synchronization, memory allocation, file systems) and profiling
Desired Skills
Exposure to CPU Architecture based on ARM or x86.
Exposure to Memory architecture, through with Weakly ordered memory model and barriers concepts
RISC-V architectural knowledge would be an added plus.
Exposure to SoC architecture paradigms - interconnects, power management.
Exposure to working on emulation/pre-si environment is added advantage.
Hands on experience with JTAG based debuggers.
Bring-up of hardware-software solution on emulation platforms and on fresh SOC designs.
ASIC digital design fundamentals and methodology would be an added advantage.
Responsibilities
Able to understand various hardware modules constituting CPU sub-system and its interfaces.
Ability to work with hardware design team to develop low level drivers for early enablement.
Chalk out hardware functional validation plan, develop test bench and execute during pre and post silicon SOC bring up phases to expose HW issues.
Excellent communication skills and ability to work with diverse teams to drive HW debugs to conclusion.
Use silicon debug hooks to measure power/performance/coverage and other KPI metrics
