2024 ASIC Physical Design Engineer Intern, Annapurna Labs Amazon

Job Description Apply promptly! A high volume of applicants is expected for the role as detailed below, do not wait to send your CV. Team Overview We believe everyone should be able to participate and thrive in the economy. We believe bitcoin plays an essential role in the future of payments and the world’s economy. We believe that the status quo of...

Front-End ASIC Lead Design Engineer - Santa Clara, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

SLAC National Accelerator Laboratory seeks an Application Specific Integrated Circuit (ASIC) design engineer within the Integrated Circuits Department of the Instrumentation Division of the Technology Innovation Directorate. The IC department develops state-of-the-art, low-noise and low-power front-end Application Specific Integrated Circuits (ASICs) to...

Front-End ASIC Design Engineer - Milpitas, CA - Partially Remote Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing...

Senior ASIC Design Engineer | AI Start-up | AI interference Solutions | San Jose Are you a Senior-level Design Engineer with experience, or looking to work, in Generative AI? This is an opportunity to join a highly funded and expanding startup, working on cutting-edge projects at the forefront of autonomous driving and AI! As a senior member of the ASIC...

As a Principal Engineer/Manager, ASIC Physical Design , you will be responsible for providing technical leadership in developing novel/game-changing cellular infrastructure radio and ASIC solutions. You will be a key contributor to our solutions features, architectures, device functional specifications, and performance. Your primary responsibilities...

ASIC/RTL Design Engineer Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural...

About InnoPhase, Inc. INNOPHASE is a rapidly growing pre-IPO communications semiconductor company with headquarters in San Diego, CA, and advanced design centers in Irvine, CA, San Jose, CA, and Bangalore, India. We are pioneering a revolutionary 5G platform that will transform cellular network deployments. Utilizing our breakthrough, patented, wireless...

Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 5 Days Ago job requisition id JR1967995 NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a...

As a ASIC Physical Implementation, Principal Engineer, the successful candidate will work on a variety of advanced SERDES developments including the latest 56/112/224G standards. The digital implementation organization is seeking a motivated person responsible for the physical implementation of complex IPs and testchips across multiple process technologies...

SummaryJoin our team at Apple developing complex digital IP's for Apple's custom mixed-signal integrated circuits. We have already shipped hundreds of millions of chips into Apple's existing product lines, and are developing new chips for future product linesAs a member of our mixed-signal ASIC team, you will be responsible for crafting sophisticated digital...

RTL ASIC Design Engineers with 8 to 15+ years of experience. No of Openings: 2 Sunnyvale, CA Job Description: 8+ years of Exp with Logic design /micro-architecture / RTL coding is a must. Expertise in Verilog & System Verilog is a must. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB...

We are looking for Sr. ASIC Design Engineer to join our rapidly growing ASIC design team focused on high performance data center infrastructure ASIC design and SOC development. The ideal candidate for this role shares our passion for creating innovative technologies, and thrives in a highly dynamic, fast-paced, results-driven environment. We are looking for...

Senior ASIC Design Engineer, Memory Controller page is loaded Senior ASIC Design Engineer, Memory Controller Apply locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago job requisition id JR1979180 NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll join a group...

Senior ASIC Design Engineer, Memory Controller page is loaded Senior ASIC Design Engineer, Memory Controller Apply locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago job requisition id JR1979180 NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll join a group...

Senior ASIC Design Engineer | AI Start-up | AI interference Solutions | San Jose Are you a Senior-level Design Engineer with experience, or looking to work, in Generative AI? This is an opportunity to join a highly funded and expanding startup, working on cutting-edge projects at the forefront of autonomous driving and AI! As a senior member of the...

Artificial intelligence (AI) is transforming our world. Recogni is a system solution company that specializes in the design of industry-leading high-performance, low-power AI inferencing. Our mission is to enable multimodal Generative AI inference acceleration at scale by providing safe, sustainable, high-performance AI-driven solutions for many markets. We...

ASIC/RTL Design Engineer - Senior (US) San Jose, CA 95124 3 days Onsite 12 Months Contract HM Notes: This is general SOC Design Engineer role. RTL Integration, coding exp required. Understanding interface of IP blocks required Documentation exp Verilog and system Verilog exp will be plus Verification exp will be plus but not...

Location: San Jose, CA or Remote Will transfer H1's. Will consider relocation if needed. Responsibilities: Micro-architecture specifications and participate in specification and test plan reviews. Architect and implement complex RTL designs. Integrate CPU and other relevant IPs into the CPU sub-system. Work with the physical design team to...

ASICS Engineer Duration: 12 Months Location: Onsite (San Diego, CA) Job Description: Principal Duties & Responsibilities: Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low...