Senior ASIC Design Engineer

Nvidia has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...

We are now looking for a motivated Senior ASIC Engineer, Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in improving the netlist and timing quality of our designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us...

We are now looking for a Senior ASIC Power Engineer!NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer...

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in raising frequency of NVIDIA's designs and if you are a self-starter and highly motivated individual who loves to collaborate and find solutions to hard technical problems, join us today! NVIDIA has...

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by...

Are you looking for a SOC Design Engineer opportunity? If yes, come and join us. The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The NVIDIA System-On-Chip (SOC) group is looking for a top...

Senior Verification Engineer - Tegra page is loaded Senior Verification Engineer - Tegra Apply locations US, CA, Santa Clara time type Full time posted on Posted 2 Days Ago job requisition id JR1980777 We are now looking for a Senior Verification Engineer for our Tegra group! NVIDIA is seeking outstanding Senior Verification Engineers to verify the design...

CPU Design Methodology Engineer page is loaded CPU Design Methodology Engineer Apply locations US, OR, Hillsboro US, TX, Austin US, CA, Santa Clara time type Full time posted on Posted 7 Days Ago job requisition id JR1976410 We are now looking for a CPU Design Methodology Engineer: The complexity of chip development has greatly increased over the years. We...

RESPONSIBILITIES Establish block level specifications based on system requirements Design, simulate, implement and test analog/mixed-signal CMOS transistor level circuit designs for LIDAR application. Guide physical design team to establish optimal layout and perform post-layout analysis. Support chip level validation, test development, lab characterization,...

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high...

Description:• Microarchitecture development of IP subsystems• Perform RTL design of digital components.• Work with functional verification team to meet coverage and quality standards.• Analyze/fix Lint and CDC errors of the components.• Guarantee quality/timely deliverables meeting project’s schedule.• Help to improve/automate design...

RTL Design Engineer - Specialized (US) 12 months contract (W2) Location: San Jose, CA 95124. Hybrid (at least 3 days a week onsite)Job Description:Location: San Jose, CA - Hybrid (at least 3 days a week)KEY RESPONSIBILITIES: •Microarchitecture development of IP subsystems •Perform RTL design of digital components. •Work with functional verification...

RTL Design Engineer - Specialized (US) 12 months contract (W2) Location: San Jose, CA 95124. Hybrid (at least 3 days a week onsite)Job Description:Location: San Jose, CA - Hybrid (at least 3 days a week)KEY RESPONSIBILITIES: • Microarchitecture development of IP subsystems • Perform RTL design of digital components. • Work with functional...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

THE DUTIES:The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and client s internal IPs.Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara. Make sure to apply quickly in order to maximise your chances of being considered for an interview Read the complete job description below. On going needs additional 10 engineers in team. Position detail: SOC verification Experience level : 5-20 years Architect block and full-chip...