ASIC Design Engineer

Front-End ASIC Lead Design Engineer - Santa Clara, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

Front-End ASIC Lead Design Engineer - Santa Clara, CAUnique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

Front-End ASIC Lead Design Engineer - Santa Clara, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design...

Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 5 Days Ago job requisition id JR1967995 NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a...

ASIC/RTL Design Engineer Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural...

Senior ASIC Design Engineer, Memory Controller page is loaded Senior ASIC Design Engineer, Memory Controller Apply locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago job requisition id JR1979180 NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll join a group...

Senior ASIC Design Engineer, Memory Controller page is loaded Senior ASIC Design Engineer, Memory Controller Apply locations US, CA, Santa Clara time type Full time posted on Posted 30+ Days Ago job requisition id JR1979180 NVIDIA is looking for a Senior ASIC Design Engineer for our Memory Controller team! As a Senior ASIC Engineer, you'll join a group...

Senior ASIC Design Engineer page is loaded Senior ASIC Design Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 5 Days Ago job requisition id JR1967995 NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have a...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 10+ years of Hardware Engineering or related work experience.Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop...

Level: Experienced, Full Time Employee Responsibilities Responsibility for design of high performance and low power data processing chip Drive and deliver gate level netlist and placement in line with new computational mechanism Micro-architectural definition, writing micro-architecture specifications Write high performance / low power RTL, Synthesis...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Looking to add DV Engineers in Irvine, San Diego and Santa Clara.On going needs additional 10 engineers in team.Position detail: SOC verificationExperience level : 5-20 yearsArchitect block and full-chip verification environments using HVLs and constrained randomtechniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog,...

Physical Design Engineer – Santa Clara, California Permanent position – $120K-$160K base salary Unique opportunity to join an established international company in their North America expansion. Working from the NA headquarters, you will have the ability to be an impact player working with some other exceptionally talented people. The Physical Design...

Senior Timing Methodology Engineer page is loaded Senior Timing Methodology Engineer Apply locations US, CA, Santa Clara time type Full time posted on Posted 6 Days Ago job requisition id JR1980073 NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer...

As an Astera Labs Hardware Test Engineer, you will be part of a Hardware Engineering team that designs and manufactures products featuring Astera Labs portfolio of connectivity ASICs used in the worlds leading cloud service providers, server and network OEMs. In this role you will be responsible for test infrastructure development, installation, and support....

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with...

Responsibilities Responsible for implementation of ultra-high performance and low power data processing chip Work with RTL designers to achieve PPA goals and suggest appropriate tradeoffs Floor-planning, experimenting with placement and routing techniques for better PPA Do timing closure for very high frequency designs with possible hand placement of...

Senior CPU Design Engineer page is loaded Senior CPU Design Engineer Apply locations US, CA, Santa Clara US, TX, Austin time type Full time posted on Posted 8 Days Ago job requisition id JR1976812 We are looking for a Senior CPU Design Engineer!NVIDIA is seeking best-in-class CPU Design Engineers to design and implement the world’s leading CPU's...

Job Role Verification EngineerJob Type Contract Job Location Santa Clara CA (or) Job DescriptionVerification Engineer for Memory Controller Significant UVM SystemVerilog experience in complex test-benches Experience working with DRAM controller PHYs memory models is preferred Significant experience with general verification flows and metrics Excellent debug...